2020-04-13 16:43:04 +02:00
|
|
|
#pragma once
|
2019-07-30 21:43:52 +02:00
|
|
|
|
2019-08-02 20:23:54 +02:00
|
|
|
#include <stdint.h>
|
|
|
|
|
2019-08-05 17:59:33 +02:00
|
|
|
#include <avr/interrupt.h>
|
2019-08-02 20:23:54 +02:00
|
|
|
#include <avr/io.h>
|
2019-08-10 14:12:10 +02:00
|
|
|
#include <avr/sfr_defs.h>
|
2019-08-02 20:23:54 +02:00
|
|
|
|
2019-08-02 09:31:02 +02:00
|
|
|
#include "config.hpp"
|
2019-08-02 09:21:47 +02:00
|
|
|
#include "hardware.hpp"
|
2019-07-30 21:43:52 +02:00
|
|
|
|
|
|
|
#define FORCE_INLINE __attribute__((always_inline))
|
|
|
|
|
|
|
|
namespace uart {
|
|
|
|
|
|
|
|
namespace detail {
|
|
|
|
|
|
|
|
#if defined(__AVR_ATmega1284P__)
|
|
|
|
|
2019-08-10 14:12:10 +02:00
|
|
|
/*
|
2019-08-15 18:49:29 +02:00
|
|
|
The following works in avr-gcc 5.4.0, but is not legal C++, because ptr's are not legal constexpr's:
|
2019-08-10 14:12:10 +02:00
|
|
|
constexpr auto *foo = ptr;
|
|
|
|
|
2019-08-15 18:49:29 +02:00
|
|
|
Workaround is to store the the address of the ptr in a uintptr_t and reinterpret_cast it at call site.
|
|
|
|
The _SFR_ADDR macro in sfr_defs.h would give the address, but it does that by taking the address of the dereferenced
|
|
|
|
pointer and casts it to uint16_t, which is still not a legal constexpr.
|
|
|
|
The workaround therefore is to disable the pointer cast and dereference macro _MMIO_BYTE temporarily.
|
2019-08-10 14:12:10 +02:00
|
|
|
*/
|
|
|
|
|
2019-08-15 18:49:29 +02:00
|
|
|
#pragma push_macro("_MMIO_BYTE")
|
|
|
|
#undef _MMIO_BYTE
|
|
|
|
#define _MMIO_BYTE
|
|
|
|
|
2019-07-30 21:43:52 +02:00
|
|
|
struct Registers1 {
|
2019-08-15 18:49:29 +02:00
|
|
|
static constexpr uintptr_t IO_REG_ADDR = UDR1;
|
|
|
|
static constexpr uintptr_t CTRL_STAT_REG_A_ADDR = UCSR1A;
|
|
|
|
static constexpr uintptr_t CTRL_STAT_REG_B_ADDR = UCSR1B;
|
|
|
|
static constexpr uintptr_t CTRL_STAT_REG_C_ADDR = UCSR1C;
|
|
|
|
static constexpr uintptr_t BAUD_REG_L_ADDR = UBRR1L;
|
|
|
|
static constexpr uintptr_t BAUD_REG_H_ADDR = UBRR1H;
|
2019-07-30 21:43:52 +02:00
|
|
|
};
|
|
|
|
|
2019-08-15 18:49:29 +02:00
|
|
|
#pragma pop_macro("_MMIO_BYTE")
|
|
|
|
|
2019-07-30 21:43:52 +02:00
|
|
|
enum class ControlFlagsA1 {
|
|
|
|
MULTI_PROC_COMM_MODE = MPCM1,
|
|
|
|
SPEED_2X = U2X1,
|
|
|
|
PARITY_ERROR = UPE1,
|
|
|
|
DATA_OVER_RUN = DOR1,
|
|
|
|
FRAME_ERROR = FE1,
|
|
|
|
DATA_REG_EMPTY = UDRE1,
|
|
|
|
TRANSMIT_COMPLETE = TXC1,
|
|
|
|
RECEIVE_COMPLETE = RXC1,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum class ControlFlagsB1 {
|
|
|
|
TX_DATA_BIT_8 = TXB81,
|
|
|
|
RX_DATA_BIT_8 = RXB81,
|
|
|
|
CHAR_SIZE_2 = UCSZ12,
|
|
|
|
TX_ENABLE = TXEN1,
|
|
|
|
RX_ENABLE = RXEN1,
|
|
|
|
DATA_REG_EMPTY_INT_ENABLE = UDRIE1,
|
|
|
|
TX_INT_ENABLE = TXCIE1,
|
|
|
|
RX_INT_ENABLE = RXCIE1,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum class ControlFlagsC1 {
|
|
|
|
CLK_POLARITY = UCPOL1,
|
|
|
|
CHAR_SIZE_0 = UCSZ10,
|
|
|
|
CHAR_SIZE_1 = UCSZ11,
|
|
|
|
STOP_BIT_SEL = USBS1,
|
|
|
|
PARITY_MODE_0 = UPM10,
|
|
|
|
PARITY_MODE_1 = UPM11,
|
|
|
|
MODE_SEL_0 = UMSEL10,
|
|
|
|
MODE_SEL_1 = UMSEL11,
|
|
|
|
};
|
|
|
|
|
2019-07-30 21:51:13 +02:00
|
|
|
// clang-format off
|
|
|
|
constexpr int operator<<(const int &lhs, const ControlFlagsA1 &rhs) { return lhs << static_cast<int>(rhs); }
|
|
|
|
constexpr int operator<<(const int &lhs, const ControlFlagsB1 &rhs) { return lhs << static_cast<int>(rhs); }
|
|
|
|
constexpr int operator<<(const int &lhs, const ControlFlagsC1 &rhs) { return lhs << static_cast<int>(rhs); }
|
|
|
|
// clang-format on
|
2019-07-30 21:43:52 +02:00
|
|
|
|
|
|
|
#define HAS_UART1
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
} // namespace detail
|
|
|
|
|
|
|
|
#ifdef HAS_UART1
|
|
|
|
|
2019-08-05 20:05:59 +02:00
|
|
|
template <class cfg = Config<>, Driven driven = Driven::INTERRUPT, Mode mode = Mode::ASYNCHRONOUS>
|
2019-08-14 19:49:42 +02:00
|
|
|
class Hardware1 : public detail::BlockingHardware<detail::Registers1, detail::ControlFlagsA1, detail::ControlFlagsB1,
|
|
|
|
detail::ControlFlagsC1, cfg, mode> {
|
|
|
|
};
|
2019-08-02 18:20:06 +02:00
|
|
|
|
2019-08-14 19:49:42 +02:00
|
|
|
template <class cfg, Mode mode>
|
|
|
|
class Hardware1<cfg, Driven::INTERRUPT, mode>
|
|
|
|
: public detail::InterruptHardware<detail::Registers1, detail::ControlFlagsA1, detail::ControlFlagsB1,
|
|
|
|
detail::ControlFlagsC1, cfg, mode> {
|
2019-08-02 12:08:16 +02:00
|
|
|
public:
|
|
|
|
static void init() FORCE_INLINE
|
|
|
|
{
|
|
|
|
HardwareImpl::init();
|
2019-08-05 17:59:33 +02:00
|
|
|
sei();
|
2019-08-02 12:08:16 +02:00
|
|
|
}
|
2019-07-30 21:43:52 +02:00
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
private:
|
|
|
|
using HardwareImpl = detail::Hardware<detail::Registers1, detail::ControlFlagsA1, detail::ControlFlagsB1,
|
|
|
|
detail::ControlFlagsC1, cfg, Driven::INTERRUPT, mode>;
|
2019-08-15 18:07:11 +02:00
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
using InterruptHardwareImpl = detail::InterruptHardware<detail::Registers1, detail::ControlFlagsA1,
|
|
|
|
detail::ControlFlagsB1, detail::ControlFlagsC1, cfg, mode>;
|
2019-08-15 18:07:11 +02:00
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
// Must be friends with Uart interface to call these private handlers
|
|
|
|
template <class Driver>
|
|
|
|
friend class Uart;
|
2019-08-15 18:07:11 +02:00
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
static void rxIntHandler() FORCE_INLINE
|
|
|
|
{
|
|
|
|
InterruptHardwareImpl::rxIntHandler();
|
|
|
|
}
|
2019-08-15 18:07:11 +02:00
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
static void dataRegEmptyIntHandler() FORCE_INLINE
|
|
|
|
{
|
|
|
|
InterruptHardwareImpl::dataRegEmptyIntHandler();
|
|
|
|
}
|
|
|
|
};
|
2019-08-15 18:07:11 +02:00
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
} // namespace uart
|
2019-08-15 18:07:11 +02:00
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
//////////////////////////////////////////////////////////////////////////
|
2019-08-15 18:07:11 +02:00
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
// Forward declare interrupt functions to allow adding them as friends
|
|
|
|
extern "C" {
|
|
|
|
void USART1_RX_vect() __attribute__((signal));
|
|
|
|
void USART1_UDRE_vect() __attribute__((signal));
|
2019-08-15 18:07:11 +02:00
|
|
|
}
|
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
// clang-format off
|
|
|
|
#define REGISTER_UART1_INT_VECTORS(uart_type) \
|
|
|
|
ISR(USART1_RX_vect) \
|
|
|
|
{ \
|
|
|
|
uart_type::rxIntHandler(); \
|
|
|
|
} \
|
|
|
|
ISR(USART1_UDRE_vect) \
|
|
|
|
{ \
|
|
|
|
uart_type::dataRegEmptyIntHandler(); \
|
|
|
|
} \
|
|
|
|
struct _##uart_type { \
|
|
|
|
}
|
|
|
|
// clang-format off
|
2019-08-15 18:07:11 +02:00
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2020-04-13 16:43:04 +02:00
|
|
|
#undef FORCE_INLINE
|