2019-07-27 18:55:17 +02:00
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#pragma once
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2019-07-30 21:43:52 +02:00
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2019-08-02 09:21:47 +02:00
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#include "hardware.hpp"
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2019-07-30 21:43:52 +02:00
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#define FORCE_INLINE __attribute__((always_inline))
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namespace uart {
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namespace detail {
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#if defined(__AVR_ATmega1284P__)
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struct Registers1 {
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static constexpr volatile auto *IO_REG = &UDR1;
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static constexpr volatile auto *CTRL_STAT_REG_A = &UCSR1A;
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static constexpr volatile auto *CTRL_STAT_REG_B = &UCSR1B;
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static constexpr volatile auto *CTRL_STAT_REG_C = &UCSR1C;
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static constexpr volatile auto *BAUD_REG_L = &UBRR1L;
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static constexpr volatile auto *BAUD_REG_H = &UBRR1H;
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};
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enum class ControlFlagsA1 {
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MULTI_PROC_COMM_MODE = MPCM1,
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SPEED_2X = U2X1,
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PARITY_ERROR = UPE1,
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DATA_OVER_RUN = DOR1,
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FRAME_ERROR = FE1,
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DATA_REG_EMPTY = UDRE1,
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TRANSMIT_COMPLETE = TXC1,
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RECEIVE_COMPLETE = RXC1,
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};
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enum class ControlFlagsB1 {
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TX_DATA_BIT_8 = TXB81,
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RX_DATA_BIT_8 = RXB81,
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CHAR_SIZE_2 = UCSZ12,
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TX_ENABLE = TXEN1,
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RX_ENABLE = RXEN1,
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DATA_REG_EMPTY_INT_ENABLE = UDRIE1,
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TX_INT_ENABLE = TXCIE1,
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RX_INT_ENABLE = RXCIE1,
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};
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enum class ControlFlagsC1 {
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CLK_POLARITY = UCPOL1,
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CHAR_SIZE_0 = UCSZ10,
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CHAR_SIZE_1 = UCSZ11,
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STOP_BIT_SEL = USBS1,
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PARITY_MODE_0 = UPM10,
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PARITY_MODE_1 = UPM11,
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MODE_SEL_0 = UMSEL10,
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MODE_SEL_1 = UMSEL11,
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};
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2019-07-30 21:51:13 +02:00
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// clang-format off
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constexpr int operator<<(const int &lhs, const ControlFlagsA1 &rhs) { return lhs << static_cast<int>(rhs); }
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constexpr int operator<<(const int &lhs, const ControlFlagsB1 &rhs) { return lhs << static_cast<int>(rhs); }
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constexpr int operator<<(const int &lhs, const ControlFlagsC1 &rhs) { return lhs << static_cast<int>(rhs); }
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// clang-format on
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2019-07-30 21:43:52 +02:00
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#define HAS_UART1
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#else
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#error "This chip is not supported"
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#endif
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} // namespace detail
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#ifdef HAS_UART1
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template <Mode mode = Mode::ASYNCHRONOUS, class cfg = Config<>, Driven driven = Driven::INTERRUPT>
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class Hardware1 {
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public:
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using data_t = typename cfg::data_t;
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static constexpr auto DATA_BITS = cfg::DATA_BITS;
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2019-07-30 21:48:00 +02:00
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static void init() FORCE_INLINE
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2019-07-30 21:43:52 +02:00
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{
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HardwareImpl::init();
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}
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static void txByte(data_t byte) FORCE_INLINE
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{
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HardwareImpl::txByte(byte);
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}
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2019-07-30 21:48:00 +02:00
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static data_t rxByte() FORCE_INLINE {}
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2019-07-30 21:43:52 +02:00
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2019-07-30 21:48:00 +02:00
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static data_t peek() FORCE_INLINE {}
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2019-07-30 21:43:52 +02:00
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private:
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using HardwareImpl = detail::Hardware<detail::Registers1, detail::ControlFlagsA1, detail::ControlFlagsB1,
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detail::ControlFlagsC1, cfg, mode>;
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};
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#endif
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} // namespace uart
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#undef FORCE_INLINE
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