89 Commits

Author SHA1 Message Date
04c04abe3e tsb: vendor the fixed-baud assembly oracle as the size/feature bar
The Seed Robotics native-UART fixed-baud TinySafeBoot (GPLv3), reference
only — not built. Assembles to 500 B with the full feature set, proving
≤512 B and full feature parity are simultaneously reachable. Also drops the
stale empty stk500v2/ leftover.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-07-19 15:29:58 +02:00
f32a27ff15 tsb: use the named register surface
Direct register access now reads through the named surface
(hw::mcusr::wdrf.test(), hw::ucsr0b::write(...)) instead of the string form,
matching how libavr itself is written. Zero-overhead: pure 740 B, tricks 658 B,
asm 508 B unchanged, all byte-identical across modes, protocol green.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-19 14:55:01 +02:00
57d94cf631 tsb: refactor the pure tier onto libavr sugar
The showcase tier now leans on the helpers it fed back instead of reaching under
them: the info block is an avr::flash_table (no raw [[gnu::progmem]]), a page is
filled with spm::fill(addr, span) (no hand-packed lo|hi<<8 loop), and the
WDT-reset bail reads field<"MCUSR","WDRF">::test() (no read() & {}(1).value).

Zero-overhead throughout: .text stays 740 B, byte-identical across generated and
reflect modes, protocol test green. The info block streams through the existing
address-based send_flash rather than a range-for over the flash_table — the
range-for is a distinct loop that cannot share the loader's one flash streamer,
so it would add 14 B for no functional gain.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-19 13:33:53 +02:00
8203a24f33 tsb: slim the port branch to the libavr reimplementation
main carried the whole pre-libavr tree beside the port: the other-bootloader
directories (blink, stk500v2), the Atmel Studio solution/project, and — dead in
the tsb dir itself — four submodule links to the superseded io/flash/uart/type
libraries the libavr sources never include. None are build inputs; CMake drives
the three variants through FetchContent. master keeps the full legacy tree
untouched.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-19 13:12:56 +02:00
2906da3272 tsb: drop the local -O3 strip, now handled by the libavr toolchain
The -O3 leak is fixed upstream (cmake/release-os.cmake via CMAKE_PROJECT_INCLUDE),
so the port no longer needs its own string(REPLACE); a Release build is -Os
through the toolchain file. Verified: all three variants build at their sizes
(508/658/740) and pass the size + protocol ctest.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-19 10:52:13 +02:00
64c1e484b5 tsb: reimplement TinySafeBoot on libavr in three size tiers
The native-UART fixed-baud TinySafeBoot protocol, ported onto libavr as a
crt-free boot-section loader, in three variants that trade clarity for size:

  tsb_pure   740 B  idiomatic C++: SRAM page buffer, separate flash/EEPROM
                    leaves, shared framing; the polled `unused` guard posture.
  tsb_tricks 658 B  unified runtime-flag paths (noinline/noclone), call-saved
                    global-register page walk — attributes only, no asm.
  tsb_asm    508 B  streaming store + hand-rolled UART/SPM/EEPROM/erase loops;
                    fits the 512 B boot section (BOOTSZ=11). Trims the optional
                    password gate and WDT-reset bail — unreachable in C++ with
                    both (hand-asm is ~15 % denser). Tiers 1-2 keep them and
                    live in the 1 KB section they fit.

All three are .text byte-identical across libavr's generated and reflect modes.
The CMake build strips the leaked -O3 (a Release build is silently -O3, not the
-Os this loader is measured against) and gates each variant's size against its
section. A simavr harness (test/device.c + test/tsbtest.py) drives the real wire
protocol over a pty and flashes the device; the size and protocol tests run in
ctest. Verified byte-for-byte against the reference tsbloader_adv (C#/mono):
activate, read info, flash write + verify.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-19 05:00:51 +02:00
14ac91c815 Update uart submodule 2020-04-13 17:20:31 +02:00
621d34cc18 Update uart submodule 2020-04-13 13:08:34 +02:00
0a65626975 Update uart submodule to fix 115200 baud with 16 MHz 2020-04-13 00:22:02 +02:00
9390f7830b Add small blink example as bootloader payload test 2020-04-12 18:45:33 +02:00
b21673e326 Uncomment setting stack pointer to allow jumping into bootloader 2020-04-12 18:43:53 +02:00
3afda0ebf9 Replace function call to user code with jump 2020-04-12 16:05:16 +02:00
807b1f336f Finish bootloader by adding jump to user code 2020-04-12 15:32:31 +02:00
5f8d6a6f85 Fix chip erase followed immediately by flash programming 2020-04-12 15:12:02 +02:00
41f81247ce Improve semantics for chip erase state enum 2020-04-12 15:07:58 +02:00
a72bf67b07 Fix flash memory address being a word-address 2020-04-12 13:10:00 +02:00
3a04b1f488 Add topcard detection for avrdude 2020-04-12 12:01:53 +02:00
8979066420 Fix receiveByte timeout and add global timeout 2020-04-12 11:47:11 +02:00
6f9d8bae42 Implement writing flash memory 2020-04-12 00:15:26 +02:00
289e66160e Refactor getting bootloader size from lambda to function 2020-04-12 00:14:51 +02:00
355160dedb Increase uart receive timeout 2020-04-12 00:12:56 +02:00
b20d0aced8 Change bootloader location of debug build 2020-04-11 23:02:50 +02:00
f307eb1340 Fix bootloader size read-out 2020-04-11 23:02:16 +02:00
3ce9c60448 Refactor address variable 2020-04-11 22:25:30 +02:00
16955979a2 Implement chip erase 2020-04-11 22:19:22 +02:00
28eeca8158 Move transmitMessage to message handling part 2020-04-11 21:17:17 +02:00
03fd10860f Implement eeprom programming 2020-04-11 19:19:23 +02:00
9c24c32f3d Add reading of eeprom 2020-04-11 17:48:13 +02:00
c46ba6bbb3 Move code to bootloader section and provide custom init code 2020-04-11 16:51:09 +02:00
98d6c9720f Add flash reading functionality 2020-04-11 10:35:52 +02:00
9ba16e71e1 Fix checksum discarding high-order byte of size field 2020-04-11 10:34:40 +02:00
c5b3614733 Add reading of lock bits 2020-04-10 16:47:17 +02:00
c808c344b4 Implement basic stk500v2 protocol support 2020-04-10 16:09:41 +02:00
0e39021192 Add all stk500v2 commands 2020-04-10 10:22:28 +02:00
39c98939bd Add uart to stk500v2 2020-04-10 10:11:47 +02:00
ef42a67d10 Change clock crystal to 18.432 MHz 2020-04-10 10:06:11 +02:00
cf60d846b6 Rename solution and add stk500v2 bootloader project 2020-04-10 08:56:54 +02:00
4348759652 Implement basic tsb protocol for information command 2020-04-10 08:50:22 +02:00
8386d55813 Initial commit 2020-04-10 08:47:54 +02:00