BlackMark
f71d76a815
HALF_DUPLEX deploys a shared line per backend. The hardware USART takes the library's .half_duplex turn-around — RXD and TXD tied off-chip, each reply byte held to transmit-complete before the line can be released (m8 404 B, m328P 440, 1284P 460; the window poll runs through the outlined release-line call at 18 or 22 cycles a poll, measured off the built loops and held per chip by pureboot.window.halfduplex). The software and autobaud links fold onto the RX pin — RX == TX spells the same — and cost nothing: the frame's direction wrap is what the dropped second-pin init paid, and the worst image in the space is unchanged at the 1284s' 502 of 512, now with its one-wire twin proven equal across the exhaustive matrix. The host gains --one-wire, the echo discard a shared line requires: the adapter's echo is matched byte for byte and a reply interleaving a blind write — a loader already in session re-prompts inside the knock — is held for the reader. The device runner models the shared line by direction (drives only while the firmware's DDR reads input, decodes only while the firmware owns it, supplies the host-side echo), extends the USART pin-ownership model to RXEN's hold on RXD, and starts the pty USART from the datasheet's zeroed UCSR#B: simavr's TXEN-set reset plus its clear-UDRE-on-TXEN-drop otherwise wedges the first transmitter after a receiver-only program, which the half-duplex window gate caught as a banner that never came. v7 is tagged at its era's last commit; v8 changes nothing on the wire. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
437 lines
17 KiB
CMake
437 lines
17 KiB
CMake
# pureboot as a consumable CMake unit: the per-chip geometry, the default baud
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# ladder, and pureboot_add_loader() — the one way a loader target is created.
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# A downstream project brings its usual libavr setup (the `libavr` target and
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# the LIBAVR_MCU toolchain preset), adds this directory, and states its
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# deployment; every argument is optional (README.md):
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#
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# add_subdirectory(bootloader/pureboot)
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# pureboot_add_loader(myboot CLOCK 1000000 SERIAL software TX pb1 RX pb5)
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# Per-family geometry, deployment defaults, and the linker wrap the PC modulo
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# needs. The slot is 512 bytes on every chip. The USART flags mirror the
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# hardware inventory the loader's own static asserts check — the plain 644 is
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# the x4 family's one single-USART die (Atmel-2593).
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set(_pb_has_usart 1)
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set(_pb_has_usart1 0)
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if(LIBAVR_MCU MATCHES "^attiny13a?$")
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set(_pb_flash 1024)
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set(_pb_wrap "")
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set(_pb_page 32)
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set(_pb_hz 9600000)
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set(_pb_eeprom 64)
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set(_pb_has_usart 0)
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elseif(LIBAVR_MCU STREQUAL "attiny25")
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set(_pb_flash 2048)
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set(_pb_wrap "")
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set(_pb_page 32)
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set(_pb_hz 8000000)
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set(_pb_eeprom 128)
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set(_pb_has_usart 0)
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elseif(LIBAVR_MCU STREQUAL "attiny45")
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set(_pb_flash 4096)
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set(_pb_wrap "")
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set(_pb_page 64)
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set(_pb_hz 8000000)
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set(_pb_eeprom 256)
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set(_pb_has_usart 0)
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elseif(LIBAVR_MCU STREQUAL "attiny85")
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set(_pb_flash 8192)
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set(_pb_wrap -Wl,--pmem-wrap-around=8k)
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set(_pb_page 64)
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set(_pb_hz 8000000)
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set(_pb_eeprom 512)
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set(_pb_has_usart 0)
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elseif(LIBAVR_MCU MATCHES "^atmega48(a|p|pa)?$")
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set(_pb_flash 4096)
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set(_pb_wrap "")
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set(_pb_page 64)
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set(_pb_hz 16000000)
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set(_pb_eeprom 256)
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elseif(LIBAVR_MCU MATCHES "^atmega8a?$" OR LIBAVR_MCU MATCHES "^atmega88(a|p|pa)?$")
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set(_pb_flash 8192)
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set(_pb_wrap -Wl,--pmem-wrap-around=8k)
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set(_pb_page 64)
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set(_pb_hz 16000000)
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set(_pb_eeprom 512)
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elseif(LIBAVR_MCU MATCHES "^atmega16a?$" OR LIBAVR_MCU MATCHES "^atmega168(a|p|pa)?$")
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set(_pb_flash 16384)
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set(_pb_wrap -Wl,--pmem-wrap-around=16k)
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set(_pb_page 128)
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set(_pb_hz 16000000)
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set(_pb_eeprom 512)
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elseif(LIBAVR_MCU MATCHES "^atmega164(a|p|pa)$")
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set(_pb_flash 16384)
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set(_pb_wrap -Wl,--pmem-wrap-around=16k)
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set(_pb_page 128)
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set(_pb_hz 16000000)
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set(_pb_eeprom 512)
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set(_pb_has_usart1 1)
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elseif(LIBAVR_MCU MATCHES "^atmega32a?$" OR LIBAVR_MCU MATCHES "^atmega328p?$")
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set(_pb_flash 32768)
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set(_pb_wrap -Wl,--pmem-wrap-around=32k)
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set(_pb_page 128)
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set(_pb_hz 16000000)
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set(_pb_eeprom 1024)
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elseif(LIBAVR_MCU MATCHES "^atmega324(a|p|pa)$")
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set(_pb_flash 32768)
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set(_pb_wrap -Wl,--pmem-wrap-around=32k)
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set(_pb_page 128)
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set(_pb_hz 16000000)
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set(_pb_eeprom 1024)
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set(_pb_has_usart1 1)
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elseif(LIBAVR_MCU MATCHES "^atmega644(a|p|pa)?$")
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# 64 KiB is exactly the 16-bit byte space, so plain LPM still reaches
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# everything and the wire stays byte-addressed. The plain 644 is the
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# family's one single-USART die.
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set(_pb_flash 65536)
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set(_pb_wrap -Wl,--pmem-wrap-around=64k)
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set(_pb_page 256)
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set(_pb_hz 16000000)
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set(_pb_eeprom 2048)
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if(NOT LIBAVR_MCU STREQUAL "atmega644")
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set(_pb_has_usart1 1)
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endif()
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elseif(LIBAVR_MCU MATCHES "^atmega1284p?$")
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# 128 KiB: wire addresses are words, reads go through ELPM, and the PC's
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# modulo wrap exceeds what --pmem-wrap-around models.
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set(_pb_flash 131072)
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set(_pb_wrap "")
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set(_pb_page 256)
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set(_pb_hz 16000000)
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set(_pb_eeprom 4096)
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set(_pb_has_usart1 1)
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else()
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message(FATAL_ERROR "pureboot: no geometry for ${LIBAVR_MCU}")
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endif()
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set(_pb_slot 512)
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math(EXPR _pb_base "${_pb_flash} - ${_pb_slot}")
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math(EXPR _pb_base_hex "${_pb_base}" OUTPUT_FORMAT HEXADECIMAL)
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# Patched-vector chips hand over through the trampoline word below the slot,
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# which is also the slot's own last word — their budget is slot − 2.
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if(LIBAVR_MCU MATCHES "^atmega" AND NOT LIBAVR_MCU MATCHES "^atmega48")
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set(_pb_app 0)
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set(_pb_limit ${_pb_slot})
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else()
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math(EXPR _pb_app "${_pb_base} - 2")
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math(EXPR _pb_limit "${_pb_slot} - 2")
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endif()
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# The pins each USART owns. A bit-banged link deployed on them has to release
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# that USART before it can drive the line, and those instructions are the one
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# way the choice of pins moves the image — so a size matrix needs them as an
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# axis even though pins are otherwise immediate operands. Uniform across every
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# mega libavr covers: USART0 (the classics' un-numbered USART included) on
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# PD0/PD1, USART1 on PD2/PD3.
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set(_pb_usart0_rx pd0)
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set(_pb_usart0_tx pd1)
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set(_pb_usart1_rx pd2)
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set(_pb_usart1_tx pd3)
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# simavr names its cores after the base dies; the A revisions run on them
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# (the 644PA on the 644P core).
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set(_pb_sim_mcu ${LIBAVR_MCU})
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if(LIBAVR_MCU MATCHES "^atmega(8|16|32|48|88|164|168|644)a$")
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string(REGEX REPLACE "a$" "" _pb_sim_mcu ${LIBAVR_MCU})
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elseif(LIBAVR_MCU STREQUAL "atmega644pa")
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set(_pb_sim_mcu atmega644p)
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endif()
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# Where SRAM begins: the classic megas keep it right after the plain I/O
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# registers, the x8/x4 generations push it past their extended I/O file, and
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# the tinies match the classics. An autobaud loader keeps its measured unit
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# in GPIOR2:GPIOR1 wherever the chip has the pair (data 0x32 on the
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# t25/45/85, 0x4A from the x8 generation on) and as the first RAM object at
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# SRAM start where it does not (the t13s and classic megas). The host reads
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# whichever home applies (pureboot.py's geometry), and the unit-position
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# test holds the image to the same split.
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if(LIBAVR_MCU MATCHES "^atmega(8|16|32)a?$")
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set(_pb_ram 0x60)
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set(_pb_unit_gpior "")
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elseif(LIBAVR_MCU MATCHES "^atmega")
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set(_pb_ram 0x100)
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set(_pb_unit_gpior 0x4A)
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elseif(LIBAVR_MCU MATCHES "^attiny13")
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set(_pb_ram 0x60)
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set(_pb_unit_gpior "")
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else()
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set(_pb_ram 0x60)
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set(_pb_unit_gpior 0x32)
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endif()
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# The function runs in its caller's scope, so everything it needs crosses
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# scopes as global properties.
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set_property(GLOBAL PROPERTY PUREBOOT_BASE_HEX ${_pb_base_hex})
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set_property(GLOBAL PROPERTY PUREBOOT_APP ${_pb_app})
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set_property(GLOBAL PROPERTY PUREBOOT_WRAP "${_pb_wrap}")
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set_property(GLOBAL PROPERTY PUREBOOT_DEFAULT_HZ ${_pb_hz})
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set_property(GLOBAL PROPERTY PUREBOOT_HAS_USART ${_pb_has_usart})
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set_property(GLOBAL PROPERTY PUREBOOT_HAS_USART1 ${_pb_has_usart1})
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set_property(GLOBAL PROPERTY PUREBOOT_USART0_RX ${_pb_usart0_rx})
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set_property(GLOBAL PROPERTY PUREBOOT_USART0_TX ${_pb_usart0_tx})
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set_property(GLOBAL PROPERTY PUREBOOT_USART1_RX ${_pb_usart1_rx})
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set_property(GLOBAL PROPERTY PUREBOOT_USART1_TX ${_pb_usart1_tx})
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# The port's own build (tests, the size matrix) reads the geometry from the
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# parent scope; a downstream consumer gets the same variables for free.
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set(PUREBOOT_BASE_HEX ${_pb_base_hex} PARENT_SCOPE)
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set(PUREBOOT_PAGE ${_pb_page} PARENT_SCOPE)
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set(PUREBOOT_SLOT ${_pb_slot} PARENT_SCOPE)
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set(PUREBOOT_LIMIT ${_pb_limit} PARENT_SCOPE)
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set(PUREBOOT_EEPROM ${_pb_eeprom} PARENT_SCOPE)
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set(PUREBOOT_DEFAULT_HZ ${_pb_hz} PARENT_SCOPE)
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set(PUREBOOT_RAM_START ${_pb_ram} PARENT_SCOPE)
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set(PUREBOOT_UNIT_GPIOR "${_pb_unit_gpior}" PARENT_SCOPE)
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set(PUREBOOT_HAS_USART ${_pb_has_usart} PARENT_SCOPE)
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set(PUREBOOT_HAS_USART1 ${_pb_has_usart1} PARENT_SCOPE)
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set(PUREBOOT_SIM_MCU ${_pb_sim_mcu} PARENT_SCOPE)
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set(PUREBOOT_USART0_RX ${_pb_usart0_rx} PARENT_SCOPE)
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set(PUREBOOT_USART0_TX ${_pb_usart0_tx} PARENT_SCOPE)
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set(PUREBOOT_USART1_RX ${_pb_usart1_rx} PARENT_SCOPE)
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set(PUREBOOT_USART1_TX ${_pb_usart1_tx} PARENT_SCOPE)
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# The rates a default may pick, fastest first.
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set_property(GLOBAL PROPERTY PUREBOOT_BAUD_LADDER 115200 57600 38400 19200 9600)
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# Whether <baud> is reachable from <clock> within 2.5 %, by the same
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# best-of-U2X-and-plain divisor search libavr's solve_baud runs, so a build
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# never trips the compile-time error it is checked against. A software build
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# also needs the polled receiver's 100-cycles-a-bit floor: at low clocks the
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# U2X divisor reaches rates the bit-banged sampler cannot.
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function(pureboot_baud_feasible clock baud software outvar)
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set(${outvar} 0 PARENT_SCOPE)
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math(EXPR _cycles "${clock} / ${baud}")
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if(software AND _cycles LESS 100)
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return()
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endif()
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foreach(divisor 8 16)
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math(EXPR _step "${divisor} * ${baud}")
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math(EXPR _n "(${clock} + ${_step} / 2) / ${_step}")
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if(_n LESS 1 OR _n GREATER 4096)
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continue()
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endif()
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math(EXPR _actual "${clock} / (${divisor} * ${_n})")
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math(EXPR _delta "${_actual} - ${baud}")
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if(_delta LESS 0)
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math(EXPR _delta "-(${_delta})")
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endif()
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math(EXPR _error_bp "${_delta} * 10000 / ${baud}")
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if(_error_bp LESS_EQUAL 250)
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set(${outvar} 1 PARENT_SCOPE)
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return()
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endif()
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endforeach()
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endfunction()
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# The fastest ladder rate the clock reaches.
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function(pureboot_default_baud clock software outvar)
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get_property(_ladder GLOBAL PROPERTY PUREBOOT_BAUD_LADDER)
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foreach(baud ${_ladder})
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pureboot_baud_feasible(${clock} ${baud} ${software} _ok)
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if(_ok)
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set(${outvar} ${baud} PARENT_SCOPE)
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return()
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endif()
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endforeach()
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message(FATAL_ERROR "pureboot: no standard baud rate fits a ${clock} Hz clock within 2.5 % "
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"— pass BAUD <rate> to deploy a non-standard one")
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endfunction()
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# pureboot_add_loader(<name> [CLOCK <hz>] [BAUD <bd>]
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# [SERIAL auto|hardware|software|autobaud] [USART <n>]
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# [RX <pin>] [TX <pin>] [TIMEOUT <s>] [OSCCAL <byte>]
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# [HALF_DUPLEX])
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#
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# The loader target plus its flashable images (<name>.hex for a programmer,
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# <name>.bin for --update-loader). The resolved deployment is stamped on the
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# target as PUREBOOT_HZ / PUREBOOT_BAUD / PUREBOOT_LINK (the link spelled
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# usart0, usart1, or sw:<RX>,<TX> with a trailing @<n> where those pins are a
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# USART's own) — what a test harness speaks to it with.
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#
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# HALF_DUPLEX is the one-wire deployment, per backend: on the hardware USART
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# it enables the library's .half_duplex turn-around (RXD and TXD tied
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# together off-chip); on a software or autobaud link it puts both directions
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# on the RX pin — the same thing RX == TX spells directly.
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#
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# SERIAL autobaud measures the host's bit timing at run time, so the image
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# carries no clock and no baud: CLOCK and BAUD are not build parameters there,
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# and one binary per chip serves every F_CPU and every rate. The stamped
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# PUREBOOT_HZ/PUREBOOT_BAUD then record what a harness should *drive* it at,
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# not what it was built for.
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#
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# OSCCAL bakes a measured oscillator trim into the loader (README.md: the
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# RC-oscillator deployment answer): the byte is written at the top of run(),
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# so every reset path — the watchdog hand-over included — runs on the
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# corrected clock. Orthogonal to the backend: an autobaud build may carry it
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# purely for the application's benefit, its own link being clock-free. No
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# value, no code.
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function(pureboot_add_loader name)
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cmake_parse_arguments(PB "HALF_DUPLEX" "CLOCK;BAUD;SERIAL;USART;RX;TX;TIMEOUT;OSCCAL" "" ${ARGN})
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if(PB_UNPARSED_ARGUMENTS)
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message(FATAL_ERROR "pureboot_add_loader(${name}): unknown arguments ${PB_UNPARSED_ARGUMENTS}")
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endif()
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get_property(_hz GLOBAL PROPERTY PUREBOOT_DEFAULT_HZ)
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get_property(_base_hex GLOBAL PROPERTY PUREBOOT_BASE_HEX)
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get_property(_app GLOBAL PROPERTY PUREBOOT_APP)
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get_property(_wrap GLOBAL PROPERTY PUREBOOT_WRAP)
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get_property(_usart GLOBAL PROPERTY PUREBOOT_HAS_USART)
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get_property(_usart1 GLOBAL PROPERTY PUREBOOT_HAS_USART1)
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if(NOT PB_CLOCK)
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set(PB_CLOCK ${_hz})
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endif()
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if(NOT PB_TIMEOUT)
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set(PB_TIMEOUT 8)
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endif()
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if(NOT PB_SERIAL)
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set(PB_SERIAL auto)
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endif()
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if(DEFINED PB_USART AND NOT PB_SERIAL MATCHES "^(auto|hardware)$")
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message(FATAL_ERROR "pureboot_add_loader(${name}): USART ${PB_USART} contradicts SERIAL ${PB_SERIAL}")
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endif()
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if(DEFINED PB_USART)
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set(PB_SERIAL hardware)
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elseif(PB_SERIAL STREQUAL "hardware")
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set(PB_USART 0)
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endif()
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set(_serial_defines "")
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if(PB_SERIAL STREQUAL "hardware")
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if(PB_USART EQUAL 1 AND NOT _usart1)
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message(FATAL_ERROR "pureboot_add_loader(${name}): ${LIBAVR_MCU} has no USART1")
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elseif(NOT _usart)
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message(FATAL_ERROR "pureboot_add_loader(${name}): ${LIBAVR_MCU} has no hardware USART")
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endif()
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set(_serial_defines PUREBOOT_USART=${PB_USART})
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if(PB_HALF_DUPLEX)
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list(APPEND _serial_defines PUREBOOT_HALF_DUPLEX)
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endif()
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set(_link usart${PB_USART})
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else()
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if(PB_SERIAL STREQUAL "auto")
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if(_usart AND (PB_RX OR PB_TX))
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message(WARNING "pureboot_add_loader(${name}): RX/TX apply to the software UART, "
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"which auto does not pick on ${LIBAVR_MCU} — SERIAL software to force it")
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endif()
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if(_usart)
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set(_link usart0)
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if(PB_HALF_DUPLEX)
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set(_serial_defines PUREBOOT_HALF_DUPLEX)
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endif()
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else()
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set(PB_SERIAL software)
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endif()
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endif()
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if(PB_SERIAL MATCHES "^(software|autobaud)$")
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if(NOT PB_RX)
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set(PB_RX pb0)
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endif()
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if(PB_HALF_DUPLEX)
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# One-wire: both directions on the RX pin. RX == TX spells
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# the same deployment directly.
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if(PB_TX AND NOT PB_TX STREQUAL PB_RX)
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message(FATAL_ERROR "pureboot_add_loader(${name}): HALF_DUPLEX puts both "
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"directions on RX (${PB_RX}); TX ${PB_TX} contradicts it")
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endif()
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set(PB_TX ${PB_RX})
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endif()
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if(NOT PB_TX)
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set(PB_TX pb1)
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endif()
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foreach(_pin ${PB_RX} ${PB_TX})
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if(NOT _pin MATCHES "^p[a-h][0-7]$")
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message(FATAL_ERROR "pureboot_add_loader(${name}): pin '${_pin}' is not of the form pb1")
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endif()
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endforeach()
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if(PB_SERIAL STREQUAL "autobaud")
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set(_serial_defines PUREBOOT_AUTOBAUD PUREBOOT_RX=${PB_RX} PUREBOOT_TX=${PB_TX})
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else()
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set(_serial_defines PUREBOOT_SOFT_SERIAL PUREBOOT_RX=${PB_RX} PUREBOOT_TX=${PB_TX})
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endif()
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# sw:<RX>,<TX> as port letter and bit, upcased — with @<n> where
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# the TX pin is a USART's own TXD, since a harness driving that
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# link has to know the USART owns the pin until the loader
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# releases it.
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string(SUBSTRING ${PB_RX} 1 2 _rx_pin)
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string(SUBSTRING ${PB_TX} 1 2 _tx_pin)
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string(TOUPPER "sw:${_rx_pin},${_tx_pin}" _link)
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string(REPLACE "SW" "sw" _link ${_link})
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get_property(_tx0 GLOBAL PROPERTY PUREBOOT_USART0_TX)
|
||
get_property(_tx1 GLOBAL PROPERTY PUREBOOT_USART1_TX)
|
||
get_property(_rx0 GLOBAL PROPERTY PUREBOOT_USART0_RX)
|
||
get_property(_rx1 GLOBAL PROPERTY PUREBOOT_USART1_RX)
|
||
if(_usart AND PB_TX STREQUAL _tx0)
|
||
set(_link "${_link}@0")
|
||
elseif(_usart1 AND PB_TX STREQUAL _tx1)
|
||
set(_link "${_link}@1")
|
||
elseif(PB_TX STREQUAL PB_RX AND _usart AND PB_RX STREQUAL _rx0)
|
||
# One-wire on a USART's RXD: RXEN forces that pin's direction
|
||
# (§20.7.3), so the driven shared pin is held exactly like a
|
||
# TXD — the harness models the hold either way.
|
||
set(_link "${_link}@0")
|
||
elseif(PB_TX STREQUAL PB_RX AND _usart1 AND PB_RX STREQUAL _rx1)
|
||
set(_link "${_link}@1")
|
||
endif()
|
||
endif()
|
||
endif()
|
||
if(NOT PB_BAUD)
|
||
if(PB_SERIAL STREQUAL "software")
|
||
pureboot_default_baud(${PB_CLOCK} 1 PB_BAUD)
|
||
else()
|
||
pureboot_default_baud(${PB_CLOCK} 0 PB_BAUD)
|
||
endif()
|
||
endif()
|
||
|
||
if(PB_SERIAL STREQUAL "autobaud")
|
||
# No clock and no baud reach the image; the window is a poll budget.
|
||
set(_defines ${_serial_defines})
|
||
else()
|
||
set(_defines PUREBOOT_CLOCK_HZ=${PB_CLOCK} PUREBOOT_BAUD=${PB_BAUD} PUREBOOT_TIMEOUT=${PB_TIMEOUT}
|
||
${_serial_defines})
|
||
endif()
|
||
if(DEFINED PB_OSCCAL)
|
||
math(EXPR _osccal "${PB_OSCCAL}" OUTPUT_FORMAT DECIMAL)
|
||
if(_osccal LESS 0 OR _osccal GREATER 255)
|
||
message(FATAL_ERROR "pureboot_add_loader(${name}): OSCCAL ${PB_OSCCAL} is not one byte")
|
||
endif()
|
||
list(APPEND _defines PUREBOOT_OSCCAL=${_osccal})
|
||
endif()
|
||
|
||
add_executable(${name} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pureboot.cpp)
|
||
target_link_libraries(${name} PRIVATE libavr)
|
||
target_compile_definitions(${name} PRIVATE ${_defines})
|
||
# Codegen shaping for the loader TU only. At -Os GCC otherwise rewrites the
|
||
# byte-stream loops' counters into end-pointer forms that cost registers
|
||
# (-fno-ivopts, -fno-split-wide-types), leaves register pressure on the
|
||
# table with the default allocator (-fira-algorithm=priority), and keeps
|
||
# expression temporaries in registers (-fno-tree-ter) — but every loop body
|
||
# here contains a call, so a register held across it costs more than the
|
||
# load-immediate it saves. The set is fitted to the loader's body and has to
|
||
# be re-measured when that body changes: -fno-move-loop-invariants belonged
|
||
# here while the command loop carried four transfer bodies and costs bytes
|
||
# now that it carries one, and -fno-ivopts is fitted per backend — an
|
||
# autobaud body needs ivopts to keep the calibration countdown a single
|
||
# induction variable (without it the counter is duplicated and the
|
||
# measurement loop runs 9 cycles instead of its contracted 7), while the
|
||
# fixed-baud bodies still measure smaller with it off.
|
||
if(PB_SERIAL STREQUAL "autobaud")
|
||
target_compile_options(${name} PRIVATE
|
||
-fira-algorithm=priority -fno-tree-ter -fno-split-wide-types)
|
||
else()
|
||
target_compile_options(${name} PRIVATE
|
||
-fno-ivopts -fira-algorithm=priority -fno-tree-ter -fno-split-wide-types)
|
||
endif()
|
||
target_link_options(${name} PRIVATE -nostartfiles -Wl,--section-start=.text=${_base_hex}
|
||
-Wl,--defsym=pureboot_app=${_app} ${_wrap})
|
||
add_custom_command(TARGET ${name} POST_BUILD COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${name}>)
|
||
# The ELF is a container, never flashed: .hex for a programmer, .bin (the
|
||
# slot's bare bytes) for --update-loader.
|
||
add_custom_command(TARGET ${name} POST_BUILD
|
||
COMMAND ${CMAKE_OBJCOPY} -O ihex -R .eeprom
|
||
$<TARGET_FILE:${name}> $<TARGET_FILE:${name}>.hex
|
||
COMMAND ${CMAKE_OBJCOPY} -O binary -R .eeprom
|
||
$<TARGET_FILE:${name}> $<TARGET_FILE:${name}>.bin)
|
||
set_target_properties(${name} PROPERTIES PUREBOOT_HZ ${PB_CLOCK} PUREBOOT_BAUD ${PB_BAUD}
|
||
PUREBOOT_LINK ${_link})
|
||
endfunction()
|
||
|