BlackMark
a977e507f3
Clock, baud, serial backend (hardware USART 0/1 or the software UART on any pins) and the activation window all resolve through one CMake function, pureboot_add_loader() in pureboot/CMakeLists.txt — the unit a downstream project consumes. The default baud is the fastest standard rate within 2.5 % (the same best-divisor search libavr's solver runs), gated on software builds by the polled receiver's 100-cycles-a-bit floor; every explicit pick is re-checked by the compile's static asserts. The size matrix builds each axis that can move the image — backend x clock ladder x USART instance, per chip — against the slot budget, and two nondefault deployments run the whole protocol suite live: the 328P on its shipped 1 MHz fuses over software serial on TX=PB1/RX=PB5 (pureboot.custom), and the 644A over USART1 (pureboot.usart1). The sim runner takes -l to bridge any link, paces a fully quiet bridge toward real time (a free-running 8 M-cycle window loses the reset-race knock), and the fixture application speaks the deployment it is built for. The loader itself shed bytes on the way: the return-address high byte spelled through byteswap (the double swap folds to the one-byte pick), the info-block address composed instead of bit_cast, and libavr's new polled-UART helpers replacing the port's uart::detail reaches. Every combination fits: 458-506 B across the megas' whole matrix, 470-484 B on the tinies, 556-562 B in the 1284s' 1 KiB slot. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
311 lines
12 KiB
CMake
311 lines
12 KiB
CMake
# pureboot as a consumable CMake unit: the per-chip geometry, the default
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# baud ladder, and pureboot_add_loader() — the one way a loader target is
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# created, both by this port's own build and by a downstream project. A
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# downstream project brings its usual libavr setup (the `libavr` target and
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# the LIBAVR_MCU toolchain preset), adds this directory, and states its
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# deployment:
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#
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# add_subdirectory(bootloader/pureboot)
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# pureboot_add_loader(myboot CLOCK 1000000 SERIAL software TX pb1 RX pb5)
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#
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# Every argument is optional — CLOCK defaults to the family assumption
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# below, BAUD to the fastest standard rate the clock reaches within 2.5 %
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# (the ladder), SERIAL to the chip's hardware USART where it has one
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# (`hardware`/`software` force a backend, USART 1 picks the second
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# instance), RX/TX to pb0/pb1 for the software UART, TIMEOUT to 8 s.
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# Infeasible picks fail the build by name: libavr's baud-error and
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# software-UART cycle-floor static asserts re-check whatever is passed.
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# Per-family geometry: flash/page/EEPROM sizes and the linker wrap the PC
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# modulo needs, the loader slot (each chip's smallest boot sector — 1 KiB on
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# the word-addressed 1284s), and the deployment defaults (crystal assumption
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# on the megas, calibrated RC on the tinies). The USART flags mirror the
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# hardware inventory the loader's own static asserts check (the plain 644 is
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# the x4 family's one single-USART die, Atmel-2593).
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set(_pb_has_usart 1)
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set(_pb_has_usart1 0)
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if(LIBAVR_MCU MATCHES "^attiny13a?$")
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set(_pb_flash 1024)
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set(_pb_wrap "")
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set(_pb_page 32)
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set(_pb_hz 9600000)
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set(_pb_eeprom 64)
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set(_pb_has_usart 0)
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elseif(LIBAVR_MCU STREQUAL "attiny25")
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set(_pb_flash 2048)
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set(_pb_wrap "")
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set(_pb_page 32)
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set(_pb_hz 8000000)
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set(_pb_eeprom 128)
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set(_pb_has_usart 0)
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elseif(LIBAVR_MCU STREQUAL "attiny45")
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set(_pb_flash 4096)
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set(_pb_wrap "")
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set(_pb_page 64)
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set(_pb_hz 8000000)
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set(_pb_eeprom 256)
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set(_pb_has_usart 0)
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elseif(LIBAVR_MCU STREQUAL "attiny85")
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set(_pb_flash 8192)
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set(_pb_wrap -Wl,--pmem-wrap-around=8k)
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set(_pb_page 64)
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set(_pb_hz 8000000)
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set(_pb_eeprom 512)
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set(_pb_has_usart 0)
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elseif(LIBAVR_MCU MATCHES "^atmega48(a|p|pa)?$")
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set(_pb_flash 4096)
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set(_pb_wrap "")
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set(_pb_page 64)
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set(_pb_hz 16000000)
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set(_pb_eeprom 256)
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elseif(LIBAVR_MCU MATCHES "^atmega8a?$" OR LIBAVR_MCU MATCHES "^atmega88(a|p|pa)?$")
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set(_pb_flash 8192)
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set(_pb_wrap -Wl,--pmem-wrap-around=8k)
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set(_pb_page 64)
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set(_pb_hz 16000000)
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set(_pb_eeprom 512)
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elseif(LIBAVR_MCU MATCHES "^atmega16a?$" OR LIBAVR_MCU MATCHES "^atmega168(a|p|pa)?$")
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set(_pb_flash 16384)
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set(_pb_wrap -Wl,--pmem-wrap-around=16k)
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set(_pb_page 128)
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set(_pb_hz 16000000)
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set(_pb_eeprom 512)
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elseif(LIBAVR_MCU MATCHES "^atmega164(a|p|pa)$")
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set(_pb_flash 16384)
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set(_pb_wrap -Wl,--pmem-wrap-around=16k)
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set(_pb_page 128)
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set(_pb_hz 16000000)
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set(_pb_eeprom 512)
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set(_pb_has_usart1 1)
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elseif(LIBAVR_MCU MATCHES "^atmega32a?$" OR LIBAVR_MCU MATCHES "^atmega328p?$")
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set(_pb_flash 32768)
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set(_pb_wrap -Wl,--pmem-wrap-around=32k)
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set(_pb_page 128)
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set(_pb_hz 16000000)
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set(_pb_eeprom 1024)
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elseif(LIBAVR_MCU MATCHES "^atmega324(a|p|pa)$")
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set(_pb_flash 32768)
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set(_pb_wrap -Wl,--pmem-wrap-around=32k)
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set(_pb_page 128)
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set(_pb_hz 16000000)
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set(_pb_eeprom 1024)
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set(_pb_has_usart1 1)
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elseif(LIBAVR_MCU MATCHES "^atmega644(a|p|pa)?$")
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# 64 KiB is exactly the 16-bit byte space: plain LPM reaches everything,
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# and the smallest boot section (1 KiB) holds the loader and its staging
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# slot together (see README.md). The plain 644 is the family's one
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# single-USART die.
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set(_pb_flash 65536)
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set(_pb_wrap -Wl,--pmem-wrap-around=64k)
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set(_pb_page 256)
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set(_pb_hz 16000000)
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set(_pb_eeprom 2048)
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if(NOT LIBAVR_MCU STREQUAL "atmega644")
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set(_pb_has_usart1 1)
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endif()
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elseif(LIBAVR_MCU MATCHES "^atmega1284p?$")
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# 128 KiB: wire flash addresses are word addresses, reads go through
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# ELPM, and the PC's modulo wrap exceeds what --pmem-wrap-around models.
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# The slot is 1 KiB — this chip's own smallest boot sector; the far
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# machinery cannot fit 512 B (see README.md).
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set(_pb_flash 131072)
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set(_pb_wrap "")
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set(_pb_page 256)
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set(_pb_hz 16000000)
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set(_pb_eeprom 4096)
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set(_pb_slot 1024)
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set(_pb_limit 1024)
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set(_pb_has_usart1 1)
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else()
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message(FATAL_ERROR "pureboot: no geometry for ${LIBAVR_MCU}")
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endif()
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if(NOT DEFINED _pb_slot)
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set(_pb_slot 512)
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endif()
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math(EXPR _pb_base "${_pb_flash} - ${_pb_slot}")
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math(EXPR _pb_base_hex "${_pb_base}" OUTPUT_FORMAT HEXADECIMAL)
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# Patched-vector chips hand over through the trampoline word below the slot,
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# which is also the slot's own last word — their budget is slot − 2.
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if(LIBAVR_MCU MATCHES "^atmega" AND NOT LIBAVR_MCU MATCHES "^atmega48")
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set(_pb_app 0)
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if(NOT DEFINED _pb_limit)
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set(_pb_limit ${_pb_slot})
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endif()
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else()
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math(EXPR _pb_app "${_pb_base} - 2")
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math(EXPR _pb_limit "${_pb_slot} - 2")
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endif()
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# simavr names its cores after the base dies; the A revisions run on them
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# (the 644PA on the 644P core).
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set(_pb_sim_mcu ${LIBAVR_MCU})
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if(LIBAVR_MCU MATCHES "^atmega(8|16|32|48|88|164|168|644)a$")
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string(REGEX REPLACE "a$" "" _pb_sim_mcu ${LIBAVR_MCU})
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elseif(LIBAVR_MCU STREQUAL "atmega644pa")
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set(_pb_sim_mcu atmega644p)
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endif()
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# The function runs in its caller's scope, so everything it needs crosses
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# scopes as global properties.
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set_property(GLOBAL PROPERTY PUREBOOT_BASE_HEX ${_pb_base_hex})
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set_property(GLOBAL PROPERTY PUREBOOT_APP ${_pb_app})
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set_property(GLOBAL PROPERTY PUREBOOT_WRAP "${_pb_wrap}")
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set_property(GLOBAL PROPERTY PUREBOOT_DEFAULT_HZ ${_pb_hz})
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set_property(GLOBAL PROPERTY PUREBOOT_HAS_USART ${_pb_has_usart})
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set_property(GLOBAL PROPERTY PUREBOOT_HAS_USART1 ${_pb_has_usart1})
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# The port's own build (tests, the size matrix) reads the geometry from the
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# parent scope; a downstream consumer gets the same variables for free.
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set(PUREBOOT_BASE_HEX ${_pb_base_hex} PARENT_SCOPE)
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set(PUREBOOT_PAGE ${_pb_page} PARENT_SCOPE)
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set(PUREBOOT_SLOT ${_pb_slot} PARENT_SCOPE)
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set(PUREBOOT_LIMIT ${_pb_limit} PARENT_SCOPE)
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set(PUREBOOT_EEPROM ${_pb_eeprom} PARENT_SCOPE)
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set(PUREBOOT_DEFAULT_HZ ${_pb_hz} PARENT_SCOPE)
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set(PUREBOOT_HAS_USART ${_pb_has_usart} PARENT_SCOPE)
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set(PUREBOOT_HAS_USART1 ${_pb_has_usart1} PARENT_SCOPE)
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set(PUREBOOT_SIM_MCU ${_pb_sim_mcu} PARENT_SCOPE)
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# The fastest standard rate the clock reaches within 2.5 % — the same
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# best-of-U2X-and-plain divisor search libavr's solve_baud runs, so a
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# default never trips the compile-time error it is checked against. A
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# software build additionally requires the polled receiver's 100-cycles-a-bit
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# floor (its own static assert): at low clocks the U2X divisor still reaches
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# rates the bit-banged sampler cannot, so the backend gates the ladder.
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function(pureboot_default_baud clock software outvar)
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foreach(baud 115200 57600 38400 19200 9600)
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math(EXPR _cycles "${clock} / ${baud}")
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if(software AND _cycles LESS 100)
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continue()
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endif()
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foreach(divisor 8 16)
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math(EXPR _step "${divisor} * ${baud}")
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math(EXPR _n "(${clock} + ${_step} / 2) / ${_step}")
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if(_n LESS 1 OR _n GREATER 4096)
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continue()
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endif()
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math(EXPR _actual "${clock} / (${divisor} * ${_n})")
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math(EXPR _delta "${_actual} - ${baud}")
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if(_delta LESS 0)
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math(EXPR _delta "-(${_delta})")
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endif()
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math(EXPR _error_bp "${_delta} * 10000 / ${baud}")
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if(_error_bp LESS_EQUAL 250)
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set(${outvar} ${baud} PARENT_SCOPE)
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return()
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endif()
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endforeach()
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endforeach()
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message(FATAL_ERROR "pureboot: no standard baud rate fits a ${clock} Hz clock within 2.5 %")
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endfunction()
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# pureboot_add_loader(<name> [CLOCK <hz>] [BAUD <bd>]
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# [SERIAL auto|hardware|software] [USART <n>]
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# [RX <pin>] [TX <pin>] [TIMEOUT <s>])
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#
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# Creates the loader target plus its flashable images (<name>.hex for a
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# programmer, <name>.bin for --update-loader) and stamps the resolved
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# deployment on the target: the PUREBOOT_HZ, PUREBOOT_BAUD and PUREBOOT_LINK
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# properties (the link as usart0/usart1/sw:<RX>,<TX> — what a test harness
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# needs to speak to the build).
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function(pureboot_add_loader name)
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cmake_parse_arguments(PB "" "CLOCK;BAUD;SERIAL;USART;RX;TX;TIMEOUT" "" ${ARGN})
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if(PB_UNPARSED_ARGUMENTS)
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message(FATAL_ERROR "pureboot_add_loader(${name}): unknown arguments ${PB_UNPARSED_ARGUMENTS}")
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endif()
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get_property(_hz GLOBAL PROPERTY PUREBOOT_DEFAULT_HZ)
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get_property(_base_hex GLOBAL PROPERTY PUREBOOT_BASE_HEX)
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get_property(_app GLOBAL PROPERTY PUREBOOT_APP)
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get_property(_wrap GLOBAL PROPERTY PUREBOOT_WRAP)
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get_property(_usart GLOBAL PROPERTY PUREBOOT_HAS_USART)
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get_property(_usart1 GLOBAL PROPERTY PUREBOOT_HAS_USART1)
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if(NOT PB_CLOCK)
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set(PB_CLOCK ${_hz})
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endif()
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if(NOT PB_TIMEOUT)
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set(PB_TIMEOUT 8)
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endif()
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if(NOT PB_SERIAL)
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set(PB_SERIAL auto)
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endif()
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if(DEFINED PB_USART AND PB_SERIAL STREQUAL "software")
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message(FATAL_ERROR "pureboot_add_loader(${name}): USART ${PB_USART} contradicts SERIAL software")
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endif()
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if(DEFINED PB_USART)
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set(PB_SERIAL hardware)
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elseif(PB_SERIAL STREQUAL "hardware")
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set(PB_USART 0)
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endif()
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set(_serial_defines "")
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if(PB_SERIAL STREQUAL "hardware")
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if(PB_USART EQUAL 1 AND NOT _usart1)
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message(FATAL_ERROR "pureboot_add_loader(${name}): ${LIBAVR_MCU} has no USART1")
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elseif(NOT _usart)
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message(FATAL_ERROR "pureboot_add_loader(${name}): ${LIBAVR_MCU} has no hardware USART")
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endif()
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set(_serial_defines PUREBOOT_USART=${PB_USART})
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set(_link usart${PB_USART})
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else()
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if(PB_SERIAL STREQUAL "auto")
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if(_usart AND (PB_RX OR PB_TX))
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message(WARNING "pureboot_add_loader(${name}): RX/TX apply to the software UART, "
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"which auto does not pick on ${LIBAVR_MCU} — SERIAL software to force it")
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endif()
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if(_usart)
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set(_link usart0)
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else()
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set(PB_SERIAL software)
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endif()
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endif()
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if(PB_SERIAL STREQUAL "software")
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if(NOT PB_RX)
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set(PB_RX pb0)
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endif()
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if(NOT PB_TX)
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set(PB_TX pb1)
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endif()
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foreach(_pin ${PB_RX} ${PB_TX})
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if(NOT _pin MATCHES "^p[a-h][0-7]$")
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message(FATAL_ERROR "pureboot_add_loader(${name}): pin '${_pin}' is not of the form pb1")
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endif()
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endforeach()
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set(_serial_defines PUREBOOT_SOFT_SERIAL PUREBOOT_RX=${PB_RX} PUREBOOT_TX=${PB_TX})
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# The link spec a test harness drives a GPIO bridge with: sw:<RX>,<TX>
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# as the port letter and bit, the loader's own pin naming upcased.
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string(SUBSTRING ${PB_RX} 1 2 _rx_pin)
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string(SUBSTRING ${PB_TX} 1 2 _tx_pin)
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string(TOUPPER "sw:${_rx_pin},${_tx_pin}" _link)
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string(REPLACE "SW" "sw" _link ${_link})
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endif()
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endif()
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if(NOT PB_BAUD)
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if(PB_SERIAL STREQUAL "software")
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pureboot_default_baud(${PB_CLOCK} 1 PB_BAUD)
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else()
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pureboot_default_baud(${PB_CLOCK} 0 PB_BAUD)
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endif()
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endif()
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set(_defines PUREBOOT_CLOCK_HZ=${PB_CLOCK} PUREBOOT_BAUD=${PB_BAUD} PUREBOOT_TIMEOUT=${PB_TIMEOUT}
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${_serial_defines})
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add_executable(${name} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pureboot.cpp)
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target_link_libraries(${name} PRIVATE libavr)
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target_compile_definitions(${name} PRIVATE ${_defines})
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target_link_options(${name} PRIVATE -nostartfiles -Wl,--section-start=.text=${_base_hex}
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-Wl,--defsym=pureboot_app=${_app} ${_wrap})
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add_custom_command(TARGET ${name} POST_BUILD COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${name}>)
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# The ELF is a container (symbols, section headers), never flashed; the
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# flashable forms sit beside it: .hex for a programmer, .bin (the slot's
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# bare bytes) for the host tool's raw path and --update-loader.
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add_custom_command(TARGET ${name} POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -O ihex -R .eeprom
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$<TARGET_FILE:${name}> $<TARGET_FILE:${name}>.hex
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COMMAND ${CMAKE_OBJCOPY} -O binary -R .eeprom
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$<TARGET_FILE:${name}> $<TARGET_FILE:${name}>.bin)
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set_target_properties(${name} PROPERTIES PUREBOOT_HZ ${PB_CLOCK} PUREBOOT_BAUD ${PB_BAUD}
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PUREBOOT_LINK ${_link})
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endfunction()
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