BlackMark a5b42bc02f test: the exhaustive clock x baud x backend size matrix ...

Every plausible oscillator against every rate it reaches against every
backend, on one chip per size-bearing class, under --full only. The baud
ladder becomes a reachability predicate the enumeration filters on, so an
unreachable point drops out instead of aborting the configure.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-07-22 23:32:28 +02:00

oracle

tsb: third size pass — restructure to the oracle's shape

2026-07-20 01:00:27 +02:00

pureboot

test: the exhaustive clock x baud x backend size matrix

2026-07-22 23:32:28 +02:00

test

pureboot 3: a 512-byte slot on every chip, the 1284s included

2026-07-22 20:49:23 +02:00

tools

test: the exhaustive clock x baud x backend size matrix

2026-07-22 23:32:28 +02:00

tsb

tsb: third size pass — restructure to the oracle's shape

2026-07-20 01:00:27 +02:00

.clang-format

tsb: reimplement TinySafeBoot on libavr in three size tiers

2026-07-19 05:00:51 +02:00

.gitattributes

Initial commit

2020-04-10 08:47:54 +02:00

.gitignore

pureboot: gitignore python bytecode cache

2026-07-20 10:43:56 +02:00

CMakeLists.txt

test: the exhaustive clock x baud x backend size matrix

2026-07-22 23:32:28 +02:00

CMakePresets.json

build: generated presets and a check entry point

2026-07-21 23:42:57 +02:00

LICENSE

Initial commit

2020-04-10 08:47:54 +02:00

Description

No description provided

1.5 MiB

Languages

C++ 100%