BlackMark
9cbe2d682d
The chip table becomes family blocks covering all 37 targets. The m48s are a new deployment class: no boot section, so the tiny profile spoken over the hardware USART — host-patched reset vector, trampoline hand-over, a 510-byte budget (474 B built), no fuse preflight — while their RWWSRE store stays the buffer discard (Atmel-8271 §26.2); the device keys the patch flag and the CPU-halt waits on the curated boot-section capability and the discard on the RWWSRE bit itself. The 644s' 64 KiB is exactly the 16-bit byte space: plain LPM, byte wire addresses, 498 B in a 512-byte slot — and their 1 KiB minimum boot section holds the resident and staging slots together, so self-update needs no fuse step (the update test's slot pick now keys word-flash on base >= 64 KiB; base + slot merely touching the boundary stays byte-addressed). The 1284 joins the 1284P's word-addressed 1 KiB slot at 558 B. BOOT_FUSE gains every boot-sectioned family's ladder and fuse byte; the planner exercises them all. The sim scaffolding keys patch-vector-ness instead of the atmega name prefix, the fixture app picks its clock by family (the tiny25/45/13 builds surfaced the 16 MHz fallthrough as garbled banners), and the runner's wrapped flash ioctl performs the m48 discard simavr's no-RWW cores turn into a stray buffer fill. Sizes across the fleet: 466-504 B megas, 474 B m48s, 498 B 644s, 488-502 B tinies, 558 B 1284s — every chip passing size/pi/planner/protocol/reloc/update. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>