BlackMark
82a31d4f16
The host tool was standard-library-only but POSIX-only with it: termios and select() bound the port layer, and importing termios failed outright on Windows, so the module could not even load there. Split Port into PosixPort (unchanged) and a WindowsPort over the Win32 serial API through ctypes, picked by os.name; every call site keeps the Port name. kernel32 only, so the standard-library constraint holds. Windows has no select() for a COM handle, so the read deadlines move into the driver as COMMTIMEOUTS, re-armed per read: read_available() ends on a gap longer than a USB-serial latency timer coalesces (16 ms on FTDI parts), read_exact() on the count or its deadline. Opening asserts DTR and RTS as a POSIX open does, so a board wiring DTR to reset still pulses it. A failed configuration closes the handle before raising - a COM handle is exclusive, and the leak met the next open as "Access is denied". Win32 takes any integer baud and a driver may accept one its hardware cannot produce (an FT232R reports back a baud of 3 and keeps the old divisor), so obvious nonsense is refused where termios' table would have. Tested against an ATmega328P on COM6: info, fuses, both memories programmed and verified, session reconnect, hand-over, the loader self-update, and the write guard on its own slot. test_planner runs on Windows now as well. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
204 lines
11 KiB
Markdown
204 lines
11 KiB
Markdown
# pureboot
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A serial bootloader on [libavr](https://git.blackmark.me/avr/libavr), pure by
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constraint: one C++ source, no inline assembly, no global register variables
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(attributes allowed), built for every chip libavr targets, **512 bytes on
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each** — 488 B on the ATtiny13A, 502 B on the ATtiny85, 504 B on the
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ATmega328P. The device speaks primitives; every composite — verify, erase,
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reset-vector surgery, updating the loader itself — lives in the host tool
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(`pureboot.py`).
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The image is **position-independent**: control flow is PC-relative, the
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read/write paths take wire addresses, the write guard protects the 512-byte
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slot the code is *running* in (from the runtime return address), the info
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block is addressed from that same anchor, and the application jump is an
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indirect call to an absolute entry. The identical binary therefore runs from
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any 512-byte slot with every command intact — which makes pureboot **its own
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staging loader**: the host installs the same binary one slot below the
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resident, jumps into it, and lets it rewrite the resident. On the tinies the
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budget is 510, not 512: a slot's last word belongs to the host-managed
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trampoline (below).
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## Link
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| Chip | Serial | Baud | Clock assumed |
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|---|---|---|---|
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| ATmega328P | USART0, RXD/TXD = PD0/PD1 | 115200 8N1 | 16 MHz crystal |
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| ATtiny85 | software UART, RX = PB0, TX = PB1 | 57600 8N1 | 8 MHz internal RC |
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| ATtiny13A | software UART, RX = PB0, TX = PB1 | 57600 8N1 | 9.6 MHz internal RC |
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The tiny RX pin has its pull-up enabled; TX idles high. All multi-byte
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quantities on the wire are little-endian.
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## Activation
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Reset enters the loader (BOOTRST on the mega, the patched reset vector on the
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tinies) — except a watchdog reset, which hands straight to the application
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(the application owns its watchdog; it must clear WDRF itself, which also
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releases the WDRF-forced WDE).
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The host then has one activation window per awaited byte to knock: `p` then
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`b`. Each awaited byte gets a fresh window; any other byte is discarded and
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awaited again (line noise cannot lock the loader, only delay it). A window
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expiring with an idle line boots the application.
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The window length is a compile-time constant — 8 s by default, another value
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via the `PUREBOOT_TIMEOUT` CMake cache variable — so the whole EEPROM belongs
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to the application; pureboot never uses it for its own state. Re-timing a
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deployed loader is a self-update with a re-timed build (below).
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## Session
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After the knock the loader stays in its command loop until `J` jumps away or
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the chip resets. Before reading each command it waits for any pending EEPROM
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write to finish and sends the prompt `+` (0x2b) — the prompt is therefore
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also the completion ack of the previous command. A session is: await `+`,
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send a command, read its reply, repeat.
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| Cmd | Arguments | Reply |
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| `b` | — | the 12-byte info block |
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| `R` | addr16, n8 | n flash bytes (n = 0 means 256) |
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| `W` | addr16, then one page of data | — (completion = next prompt) |
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| `r` | addr16, n8 | n EEPROM bytes (n = 0 means 256) |
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| `w` | addr16, n8, then n data bytes | `+` per byte, sent once its write has begun |
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| `F` | — | 4 bytes: low fuse, lock, extended fuse, high fuse |
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| `J` | word address (16-bit) | `+`, then execution continues there |
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| other | — | ignored; the loop re-prompts (send a junk byte, await `+`, to resync) |
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`W` streams exactly one SPM page (size from the info block) into the buffer,
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then erases and programs; the address must be page-aligned. Pages inside the
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512-byte slot the loader is *running* in are drained but never programmed — a
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broken host cannot brick the running copy, and a staged copy may rewrite the
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resident slot. `w` is host-paced: send the next byte only after the previous
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byte's `+`. `F` returns the bytes in the hardware's Z order; on a chip
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without an extended fuse byte (the ATtiny13A) that slot carries no meaning.
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Fuse *writing* does not exist: SPM reaches flash (and, on the mega, lock
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bits) only — fuse bytes are external-programming territory by hardware.
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`J` is the one control-transfer primitive: the host uses it to run the
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application (word 0 on the mega, the trampoline word on the tinies — both
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known from the info block) and to move between loader copies during a
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self-update. A jump to a loader slot's base re-enters that copy's own
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startup; it must then be knocked afresh.
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The info block (`b`):
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| Offset | Content |
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|---|---|
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| 0–2 | `'P'`, `'B'`, protocol version (1) |
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| 3–5 | device signature |
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| 6 | SPM page size in bytes |
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| 7–8 | loader base — application flash ends here |
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| 9–10 | EEPROM size |
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| 11 | bit 0 set: host must patch the reset vector (no hardware boot section) |
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Composites are the host's job: verify = read back and compare, erase =
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write `0xff` (per page for flash, per byte for EEPROM).
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## Deployment
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**ATmega328P**: program the loader at 0x7e00 with an external programmer.
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Two fuse profiles, same binary:
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| BOOTSZ | BOOTRST | Behavior |
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|---|---|---|
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| 256 words (512 B) | programmed | *Standalone*: reset always enters the loader; **self-update impossible** (the staging slot lies outside the boot section, where SPM is disabled). |
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| 512 words (1 KB) | unprogrammed | *Self-update, app-first*: reset always boots the application, which owns all 31.5 KB and must offer its own jump to 0x7e00 to reach the loader (a virgin chip reaches it by reset across erased flash). Updates are power-fail-safe except mid-rewrite of the resident slot itself (no reset path leads to the staging copy then). |
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| 512 words (1 KB) | programmed | *Self-update, loader-first*: reset lands at 0x7c00 — the staging slot, normally erased, so execution walks up into the loader; during an update it is the staging copy itself, so a mid-rewrite power loss recovers by reset. The loss windows move to the staging install/retire page writes instead (page-write scale). The host keeps `[0x7c00, 0x7e00)` clear of application data (`--force` overrides). |
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Applications are flashed unmodified — word 0 stays the application's own
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reset vector, and the hand-over jumps to 0.
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**Tinies** (no boot section): program the loader at `flash − 512`; erased
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flash below it walks up into the loader, so a virgin chip activates. When
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flashing an application the host performs reset-vector surgery: word 0 is
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rewritten to `rjmp` to the loader base, and the application's own entry is
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re-encoded as a trampoline `rjmp` in the word just below the loader
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(`base − 2`, where the hand-over jumps). Every other vector stays the
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application's. The patched page 0 and the trampoline page are written
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*first*, so from the first write on an interrupted flash still resets into
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the loader; an erase runs top-down for the same reason.
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## Updating the loader
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`pureboot.py --update-loader new_pureboot.bin` replaces the resident loader
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with any pureboot build — a re-timed window, a newer protocol — using the
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loader itself as its own staging loader:
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1. The staging slot `[base−512, base)` is saved to a host-side state file
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(on the 1 KB tiny13A that is the whole application, vectors included).
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2. The resident installs the identical update image there. On the tinies the
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host composes the slot's last word — the same address as the resident's
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trampoline — as a jump to the resident base, so even an abandoned staging
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copy times out into a loader, never into garbage.
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3. `J` enters the staging copy, which rewrites the resident slot. On the
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t85 the host first re-aims word 0 at the staging copy, so a power loss
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mid-rewrite still resets into a loader; on the t13a the staging slot
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carries the reset vector itself.
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4. `J` enters the new resident, which restores the staging slot's saved
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content (word 0 and the trampoline with it) and the state file is
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discarded.
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Every phase is idempotent and keyed off the actual flash state: re-running
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the same command after any interruption resumes and completes. The state
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file carries the only bytes not recoverable from the device; if it is lost
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mid-update the update still completes, and the staging region is restored by
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reflashing the application. The mega needs its fuses for the preflight
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(BOOTSZ gate, profile notes) — read from the device, or supplied with
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`--assume-fuses` where reading is impossible (simulators).
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## Host tool
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`pureboot.py` — Python 3, standard library only. The port layer is the one
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platform-specific part: termios drives any tty on POSIX (a USB adapter as
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well as a simavr pty), the Win32 serial API through `ctypes` drives a COM
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port on Windows (`--port COM6`; the `\\.\` form for two-digit ports is
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supplied by the tool). Opening the port asserts DTR and RTS on both, so a
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board that wires DTR to reset gets its reset pulse and opens the activation
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window by itself.
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pureboot.py --port /dev/ttyUSB0 --baud 57600 \
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--info --fuses --flash app.hex
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Operations run in a fixed order within one session: info, fuses, loader
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update, flash (erase / program / read / verify), EEPROM (erase / program /
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read / verify) — then the loader hands over to the application; `--stay`
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keeps the session alive instead, and a later invocation reconnects into it
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(the knock converges there too). `--flash` and `--eeprom` verify by
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read-back unless `--no-verify`; images are raw binary, or Intel HEX by
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extension. `--force` overrides the refusable safety checks (today: flashing
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application data into a mega's reset walk region).
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## Tests
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Per chip preset, `ctest` runs:
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- `pureboot.size` — the 510-byte (tinies) / 512-byte (mega) budget;
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- `pureboot.pi` — the position-independence lint: no absolute `jmp`/`call`
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in the image, the info block within its first 256 bytes;
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- `pureboot.planner` — the host tool's pure logic: programming orders and
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their recovery properties, the surgery, the staging composition, the
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boot-fuse decode, and the update preflight's error/warning matrix over
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synthetic fuse bytes;
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- `pureboot.protocol` — end to end against a simavr device
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(`test/pureboot_device.c` — the mega's USART as a pty; on the tinies a
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cycle-timed GPIO⇄pty bridge for the software UART, plus the SPM/NVM module
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simavr's tiny cores lack) driven by the real host tool through
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knock-from-reset, program + verify of both memories, session reconnect, an
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external reset through the patched vector, and the hand-over to a fixture
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application whose banner proves the launch — cross-checked against the
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simulator's ground-truth memory dumps and an independent decode of the
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surgery's rjmp words;
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- `pureboot.reloc` — the identical image installed one slot below the
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resident serves the complete command set from there (the
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position-independence acceptance test);
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- `pureboot.update` — the full `--update-loader` flow to a re-timed build,
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then every power-fail phase: the device is killed mid-write, restarted
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from its flash dump, and a re-run must complete the update with the
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application intact throughout.
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`size`, `pi`, and `planner` are host logic and run anywhere; the three
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simulator-driven targets need simavr and a pty, so they are POSIX-only —
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on Windows the tool is exercised against real hardware.
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