The chip table becomes family blocks covering all 37 targets. The m48s are a new deployment class: no boot section, so the tiny profile spoken over the hardware USART — host-patched reset vector, trampoline hand-over, a 510-byte budget (474 B built), no fuse preflight — while their RWWSRE store stays the buffer discard (Atmel-8271 §26.2); the device keys the patch flag and the CPU-halt waits on the curated boot-section capability and the discard on the RWWSRE bit itself. The 644s' 64 KiB is exactly the 16-bit byte space: plain LPM, byte wire addresses, 498 B in a 512-byte slot — and their 1 KiB minimum boot section holds the resident and staging slots together, so self-update needs no fuse step (the update test's slot pick now keys word-flash on base >= 64 KiB; base + slot merely touching the boundary stays byte-addressed). The 1284 joins the 1284P's word-addressed 1 KiB slot at 558 B. BOOT_FUSE gains every boot-sectioned family's ladder and fuse byte; the planner exercises them all. The sim scaffolding keys patch-vector-ness instead of the atmega name prefix, the fixture app picks its clock by family (the tiny25/45/13 builds surfaced the 16 MHz fallthrough as garbled banners), and the runner's wrapped flash ioctl performs the m48 discard simavr's no-RWW cores turn into a stray buffer fill. Sizes across the fleet: 466-504 B megas, 474 B m48s, 498 B 644s, 488-502 B tinies, 558 B 1284s — every chip passing size/pi/planner/protocol/reloc/update. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
486 lines
18 KiB
C++
486 lines
18 KiB
C++
// pureboot — a serial bootloader on libavr, pure by constraint: one C++
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// source with no inline assembly and no global register variables, built for
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// every chip libavr targets, 512 bytes on each. The device speaks primitives
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// — read/program flash, read/write EEPROM, fuse bytes, an info block, a jump
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// — and everything composite (verify, erase, reset-vector surgery, updating
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// the loader itself) lives in the host tool. Protocol reference: README.md
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// next to this file.
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//
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// The image is position-independent: control flow is PC-relative, the write
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// and read paths take wire addresses, the write guard refuses the 512-byte
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// slot the code is *running* in (taken from the runtime return address), the
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// info block is read relative to that same anchor, and the application jump
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// is an indirect call to an absolute entry. The identical binary therefore
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// runs from any 512-byte slot with every command intact: flashed one slot
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// below the resident loader it becomes the staging loader that rewrites the
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// resident — how pureboot updates itself, host-driven, with no other
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// firmware involved.
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//
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// Entry: reset lands in avr::startup::entry below (BOOTRST on the
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// boot-sectioned megas; the patched reset vector — or erased flash walking
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// up into the loader — on the tinies and the boot-section-less m48s). A
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// watchdog reset hands straight to the application. Otherwise the
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// host has one activation window per awaited knock byte ("pb"); an idle line
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// boots the application. A session then stays in the command loop until 'J'
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// jumps away or the chip resets.
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#include <libavr/libavr.hpp>
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using namespace avr::literals;
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namespace spm = avr::spm;
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namespace ee = avr::eeprom;
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namespace pureboot {
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namespace {
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// Purely polled — interrupts stay off, every guard folds to nothing.
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constexpr auto off = avr::irq::guard_policy::unused;
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constexpr std::uint8_t ack = '+';
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// Per-chip personality: the clocks the dogfood boards run (16 MHz crystal on
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// the mega, calibrated RC on the tinies). The device signature comes straight
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// from the chip database (avr::hw::db.signature) — compile-time data is the
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// only universal source, since the tiny13A cannot even read its signature row
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// from code.
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consteval avr::hertz_t clock()
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{
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auto name = std::string_view{avr::hw::db.name};
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if (name.starts_with("ATtiny13"))
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return 9.6_MHz;
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if (name.starts_with("ATtiny"))
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return 8_MHz;
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return 16_MHz;
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}
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using dev = avr::device<{.clock = clock()}>;
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// The watchdog reset flag's home: MCUSR, or the classic megas' MCUCSR.
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consteval std::int16_t wdrf_field()
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{
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auto reg = std::string_view{avr::hw::db.regs[static_cast<std::size_t>(avr::power::detail::reset_reg())].name};
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return avr::hw::db.field_index(reg, "WDRF");
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}
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// Geometry: the resident loader owns the top slot of flash — 512 bytes,
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// except on the >64 KiB chips whose own smallest boot sector is 1 KiB (the
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// 1284s): there the slot is 1 KiB, matching the hardware boundary the
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// 512-byte figure comes from everywhere else. The word below the slot is
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// the trampoline (the application's relocated reset vector) on chips
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// without a hardware boot section — the tinies and the m48s, whose SPM
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// runs from anywhere (Atmel-8271 §26). A boot section also means the CPU
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// runs on while the RWW section programs; everywhere else it halts through
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// the operation. The m48s still carry RWWSRE as their temporary-buffer
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// discard (§26.2), so the discard picks by that bit, not by the section.
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constexpr std::uint16_t slot_bytes = spm::flash_bytes > 65536 ? 1024 : 512;
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constexpr std::uint32_t base = spm::flash_bytes - slot_bytes;
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constexpr std::uint16_t page = spm::page_bytes;
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constexpr bool boot_section = avr::hw::curated::has_boot_section();
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constexpr bool rww_discard = spm::detail::has_rww();
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// Past 64 KiB a byte address no longer fits the wire's 16 bits, so on the
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// large chips every flash address on the wire — and all slot arithmetic —
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// is a word address instead ('J' always was one). A slot spans the same
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// wire-high-byte pair in either unit (512 B = 2 x 256 bytes, 1 KiB =
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// 2 x 256 words), so the slot index is the high byte with its low bit
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// dropped everywhere.
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constexpr bool word_flash = spm::flash_bytes > 65536;
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constexpr std::uint16_t wire_base =
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word_flash ? static_cast<std::uint16_t>(base / 2) : static_cast<std::uint16_t>(base);
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constexpr std::uint16_t wire_page_mask = word_flash ? (page / 2 - 1) : (page - 1);
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// The activation window, in seconds, is a compile-time constant (the build
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// may override it): the whole EEPROM belongs to the application, and
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// re-timing the loader is a bootloader self-update with a re-timed binary.
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#if !defined(PUREBOOT_TIMEOUT)
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#define PUREBOOT_TIMEOUT 8
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#endif
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constexpr std::uint8_t timeout_seconds = PUREBOOT_TIMEOUT;
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// The 12-byte info block the host reads with the 'b' command; flash-resident
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// (there is no crt to copy a .data image), word-aligned so its wire (word)
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// address is exact on the large chips. The page byte is the wire count
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// convention: 0 means 256.
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[[gnu::progmem]] alignas(2) inline constexpr std::array<std::uint8_t, 12> info_data = {
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'P',
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'B',
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1, // magic, protocol version
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avr::hw::db.signature[0],
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avr::hw::db.signature[1],
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avr::hw::db.signature[2],
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static_cast<std::uint8_t>(page),
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wire_base & 0xff,
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wire_base >> 8, // app flash ends here; resident loader base (a word address on large chips)
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avr::hw::db.mem.eeprom_size & 0xff,
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avr::hw::db.mem.eeprom_size >> 8,
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// bit 0: host must patch the reset vector (no hardware boot section);
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// bit 1: flash wire addresses are word addresses
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static_cast<std::uint8_t>((boot_section ? 0 : 1) | (word_flash ? 2 : 0)),
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};
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// The serial link: the hardware USART where the chip has one, the polled
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// software UART (no vector — the table belongs to the application) on PB0/PB1
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// elsewhere. Both are class templates on the clock so only the selected
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// backend is ever instantiated. pending() is the cheap line test the
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// activation window polls; rx() then picks the byte up; drain() holds until
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// the last transmitted frame is fully on the wire (the jump hand-over must
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// not let the target's re-init clip the ack).
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template <avr::hertz_t C>
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consteval std::int16_t rxc_field()
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{
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return avr::uart::detail::ufield<'0', "UCSR#A", "RXC#">();
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}
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template <avr::hertz_t C>
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consteval std::int16_t txc_field()
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{
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return avr::uart::detail::ufield<'0', "UCSR#A", "TXC#">();
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}
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template <avr::hertz_t C>
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consteval std::int16_t status_reg()
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{
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return avr::uart::detail::ureg<'0', "UCSR#A">();
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}
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template <avr::hertz_t C>
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struct hardware_link {
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using uart = avr::uart::usart0<C, {.baud = 115200_Bd, .max_baud_error = 2.5_pct}>;
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// The compiled idle poll: lds UCSR0A (2), sbrc skipping the exit (2),
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// sbiw + sbci + sbci + brne (6).
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static constexpr std::uint8_t poll_cycles = 10;
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static void init()
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{
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avr::init<uart>();
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}
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static bool pending()
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{
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return avr::hw::field_impl<rxc_field<C>()>::test();
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}
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static std::uint8_t rx()
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{
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return uart::read_blocking();
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}
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static void tx(std::uint8_t byte)
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{
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uart::write(byte);
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}
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static void drain()
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{
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// write() leaves the byte draining behind it. Clear a stale TXC0
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// first (W1C by writing the sampled status back — the store a hand
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// assembler writes, keeping U2X0), then wait for the fresh
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// completion; with a byte still ahead in the shifter TXC0 cannot
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// re-set until the last pending byte has fully left.
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using status = avr::hw::reg_impl<status_reg<C>()>;
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status::write(status::read());
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while (!avr::hw::field_impl<txc_field<C>()>::test()) {
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}
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}
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};
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template <avr::hertz_t C>
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struct software_link {
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using rx_t = avr::uart::software_rx_polled<C, avr::pb0, 57600_Bd>;
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using tx_t = avr::uart::software_tx<C, avr::pb1, 57600_Bd>;
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// The compiled idle poll: sbis skipping the exit (2), sbiw + sbci +
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// sbci + brne (6).
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static constexpr std::uint8_t poll_cycles = 8;
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static void init()
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{
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avr::init<rx_t, tx_t>();
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}
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static bool pending()
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{
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return !avr::io::input<avr::pb0>::read(); // a start bit has begun
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}
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static std::uint8_t rx()
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{
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return rx_t::template read_blocking<off>();
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}
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static void tx(std::uint8_t byte)
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{
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tx_t::template write<off>(byte);
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}
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static void drain()
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{
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// The software transmitter returns only after the stop bit.
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}
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};
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using link = std::conditional_t<avr::hw::db.has_instance("USART0") || avr::hw::db.has_instance("USART"),
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hardware_link<dev::clock>, software_link<dev::clock>>;
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// The application's entry, an absolute address the linker pins (--defsym in
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// CMakeLists.txt): 0x0000 on the mega (word 0 stays the application's own
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// vector — BOOTRST re-vectors a reset into the loader in hardware) and the
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// trampoline word at base - 2 on the tinies. Reaching it must not depend on
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// where this copy runs, so the jump goes through a pointer: [[gnu::noipa]]
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// keeps the constant from folding back into a PC-relative call.
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extern "C" [[noreturn]] void pureboot_app();
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[[gnu::noipa, noreturn]] void jump(void (*target)())
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{
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target();
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__builtin_unreachable();
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}
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[[gnu::noinline, noreturn]] void run_app()
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{
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jump(pureboot_app);
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}
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// One activation window is a single 32-bit poll countdown. The divisor is
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// the backend's counted poll-loop cycles (its own comment reads them off the
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// compiled loop); whole-second precision is all the window promises, so the
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// nearest cycle count is plenty.
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consteval std::uint32_t window_polls()
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{
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return timeout_seconds * static_cast<std::uint32_t>(dev::clock.hz / link::poll_cycles);
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}
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bool pending_before_deadline()
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{
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std::uint32_t polls = window_polls();
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do {
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if (link::pending())
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return true;
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} while (--polls);
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return false;
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}
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// A knock byte under the activation deadline: an idle line means no host is
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// there, and the application runs.
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std::uint8_t rx_deadline()
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{
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if (!pending_before_deadline())
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run_app();
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return link::rx();
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}
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std::uint16_t rx16()
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{
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std::uint16_t low = link::rx();
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return static_cast<std::uint16_t>(low | (link::rx() << 8));
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}
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// The streamers take the count in the wire's 8-bit form: 0 means 256.
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// send_flash stays out of line: its two callers ('b' and 'R') otherwise each
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// inline a private copy of the loop. On the large chips the address is a
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// word address and the read goes through ELPM (flash_load_far).
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[[gnu::noinline]] void send_flash(std::uint16_t address, std::uint8_t count)
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{
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if constexpr (word_flash) {
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// The 24-bit cursor as the machine holds it: the RAMPZ byte and a
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// 16-bit Z, carried explicitly (the reassembled 32-bit address
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// folds away inside the inlined far load). A single read never
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// crosses a 64 KiB boundary — the protocol forbids it and the host
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// splits its chunks there — so RAMPZ holds for the whole run.
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std::uint8_t rampz = static_cast<std::uint8_t>(address >> 15);
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std::uint16_t z = static_cast<std::uint16_t>(address << 1);
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do {
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link::tx(avr::flash_load_far<std::uint8_t>((static_cast<std::uint32_t>(rampz) << 16) | z));
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if (++z == 0)
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++rampz; // robustness for a host that reads across 64 KiB
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} while (--count);
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} else {
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do
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link::tx(avr::flash_load(reinterpret_cast<const std::uint8_t *>(address++)));
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while (--count);
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}
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}
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void send_eeprom(std::uint16_t address, std::uint8_t count)
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{
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do
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link::tx(ee::read(address++));
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while (--count);
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}
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// EEPROM write, host-paced: each ack goes out once the byte's write has
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// begun, so the next byte arrives while it completes and the following
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// write's own ready-wait sees an idle line. Nothing is ever missed, on
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// either serial backend, without a buffer.
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void store_eeprom(std::uint16_t address, std::uint8_t count)
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{
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do {
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ee::write<off>(address++, link::rx());
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link::tx(ack);
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} while (--count);
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}
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// One flash page: stream the bytes into the SPM buffer as little-endian
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// words, then erase and program — except the 512-byte slot this code runs
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// in, which is drained but never programmed, so a copy can never erase
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// itself. `slot_high` is the high byte of that running slot's base (run()
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// derives it); a broken host thus cannot brick the running loader, and a
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// copy flashed one slot lower may rewrite the slot above it — how pureboot
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// updates itself. On the mega the RWW section is re-enabled so reads work
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// immediately.
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void program_flash(std::uint16_t wire_address, std::uint8_t slot_high)
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{
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// A buffer word cannot be loaded twice without an erase (§26.2.1), so a
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// refused page's drained data must not linger for the next write:
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// discard the buffer up front — CTPB on the tinies; on the megas
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// writing RWWSRE aborts a pending load (§26.2.2 — on the m48s that
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// flush is the bit's whole documented job).
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if constexpr (rww_discard)
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spm::rww_enable<off>();
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else
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spm::clear_buffer<off>();
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// One induction either way. On the byte-addressed chips the wire address
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// itself walks the page (aligned, so the offset bits wrap to zero); on
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// the word-addressed large chips the wire word address becomes a 32-bit
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// byte cursor once, and their 256-byte page makes its low byte the whole
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// in-page offset. The slot index is one high byte of the wire address —
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// two values on byte-addressed chips (the & ~1), bits 16:9 re-packed on
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// the large ones.
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spm::flash_address_t address;
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std::uint8_t page_high;
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if constexpr (word_flash) {
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// Pages are aligned, so one page never crosses a 64 KiB boundary:
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// RAMPZ is a per-page constant and the fill cursor is a 16-bit Z
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// whose low byte is the whole in-page offset (256-byte pages). The
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// slot index is simply the wire word address's high byte.
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const std::uint8_t rampz = static_cast<std::uint8_t>(wire_address >> 15);
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const std::uint16_t z0 = static_cast<std::uint16_t>(wire_address << 1);
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std::uint16_t z = z0;
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do {
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std::uint8_t low = link::rx();
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std::uint8_t high = link::rx();
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spm::fill<off>((static_cast<spm::flash_address_t>(rampz) << 16) | z,
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static_cast<std::uint16_t>(low | (high << 8)));
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z += 2;
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} while (static_cast<std::uint8_t>(z));
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address = (static_cast<spm::flash_address_t>(rampz) << 16) | z0;
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page_high = static_cast<std::uint8_t>(wire_address >> 8) & 0xfe;
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} else {
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address = static_cast<spm::flash_address_t>(wire_address);
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do {
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std::uint8_t low = link::rx();
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std::uint8_t high = link::rx();
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spm::fill<off>(address, static_cast<std::uint16_t>(low | (high << 8)));
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address += 2;
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} while (static_cast<std::uint8_t>(address) & (page - 1));
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address -= 2; // back inside the page — erase and write ignore the word bits
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page_high = static_cast<std::uint8_t>(address >> 8) & 0xfe;
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}
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if (page_high != slot_high) {
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// The tinies and the m48s halt the CPU through the erase and the
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// write, so only the boot-sectioned megas — running on while their
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// RWW section programs — wait.
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spm::erase_page<off>(address);
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if constexpr (boot_section)
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spm::wait();
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spm::write_page<off>(address);
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if constexpr (boot_section) {
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spm::wait();
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spm::rww_enable<off>();
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}
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}
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}
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// The four fuse/lock bytes in the hardware's own Z order: low, lock,
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// extended, high. Writing fuses is not a thing self-programming can do on
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// AVR — SPM reaches flash (and boot lock bits) only.
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void send_fuses()
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{
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std::uint8_t which = 0;
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do
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link::tx(spm::read_fuse<off>(static_cast<spm::fuse>(which)));
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while (++which & 3);
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}
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[[noreturn]] void run()
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{
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// A watchdog reset belongs to the application (whose watchdog stays
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// forced on until it clears WDRF) — no activation window in its way.
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// The flag register is MCUSR, or the classic megas' MCUCSR.
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if (avr::hw::field_impl<wdrf_field()>::test())
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run_app();
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link::init();
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|
// The high byte of the 512-byte-aligned base this copy runs at: the
|
|
// return address is a word address, whose high byte is the 256-word slot
|
|
// index — on byte-addressed chips doubled back into byte terms.
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|
// program_flash refuses this one slot and the info block is addressed
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// from it, so both follow wherever the code was flashed.
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|
const std::uint16_t ra_words = reinterpret_cast<std::uint16_t>(__builtin_return_address(0));
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const std::uint8_t slot_high =
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word_flash ? static_cast<std::uint8_t>(ra_words >> 8) & 0xfe : static_cast<std::uint8_t>((ra_words >> 8) << 1);
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|
|
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// The knock: 'p' then 'b', each under a fresh window; any other byte is
|
|
// line noise and waits again. Falling out of a window runs the app.
|
|
while (rx_deadline() != 'p' || rx_deadline() != 'b') {
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|
}
|
|
|
|
for (;;) {
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|
// No prompt while an EEPROM write runs: a pending write blocks SPM
|
|
// and fuse reads (§26.2.1), and the ack tells the host all is done.
|
|
ee::wait();
|
|
link::tx(ack);
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|
const std::uint8_t command = link::rx();
|
|
switch (command) {
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|
case 'b': { // info block, read relative to the running slot
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|
// The block sits in the image's first 256 bytes (the build lint
|
|
// asserts it), and slots are 512-aligned — so the low byte of its
|
|
// link address (in wire units: bytes, or words on the large
|
|
// chips) is its offset in any slot, and the high byte of its
|
|
// runtime address is the running slot's. Built as a byte pair so
|
|
// no absolute address is ever materialized.
|
|
const auto link_low = reinterpret_cast<std::uint16_t>(info_data.data());
|
|
const std::uint8_t low =
|
|
word_flash ? static_cast<std::uint8_t>(link_low >> 1) : static_cast<std::uint8_t>(link_low);
|
|
send_flash(std::bit_cast<std::uint16_t>(std::array{low, slot_high}),
|
|
static_cast<std::uint8_t>(info_data.size()));
|
|
break;
|
|
}
|
|
case 'J': { // jump to a wire word address: hand-over and staging transfer
|
|
auto target = reinterpret_cast<void (*)()>(rx16());
|
|
link::tx(ack);
|
|
link::drain();
|
|
jump(target);
|
|
}
|
|
case 'R': // read flash: addr16, n8 (0 = 256)
|
|
case 'r': // read EEPROM: addr16, n8
|
|
case 'w': { // write EEPROM: addr16, n8, then n bytes each acked
|
|
std::uint16_t address = rx16();
|
|
std::uint8_t count = link::rx();
|
|
if (command == 'R')
|
|
send_flash(address, count);
|
|
else if (command == 'r')
|
|
send_eeprom(address, count);
|
|
else
|
|
store_eeprom(address, count);
|
|
break;
|
|
}
|
|
case 'W': // program one flash page: addr16, page bytes
|
|
program_flash(rx16(), slot_high);
|
|
break;
|
|
case 'F': // fuse and lock bytes
|
|
send_fuses();
|
|
break;
|
|
default: // unknown bytes are ignored; the loop re-acks
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
} // namespace
|
|
} // namespace pureboot
|
|
|
|
template struct avr::startup::entry<pureboot::run>;
|