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BlackMark 34e7f1be34 tsb: drive each tier to its size floor

asm 502->498 B (below the oracle's 500): the stack bring-up moves to plain C++,
and a register is reserved for the config-page high byte instead of reloading it
at each app-flash-boundary compare. tricks 808->778 B: shared erase/rww helpers
plus the libavr half-duplex W1C fix. pure 950->896 B and no SRAM: streams
rx->SPM/EEPROM instead of staging a 128 B page buffer. All three keep full oracle
feature parity and stay byte-identical across modes; protocol tests (round-trip +
password + emergency erase) green.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01UHeP42XU3wf6RfhyuxBTE5

2026-07-19 18:47:38 +02:00

oracle

tsb: vendor the fixed-baud assembly oracle as the size/feature bar

2026-07-19 15:29:58 +02:00

test

tsb: protocol test covers the password gate and emergency erase

2026-07-19 16:49:20 +02:00

tsb

tsb: drive each tier to its size floor

2026-07-19 18:47:38 +02:00

.clang-format

tsb: reimplement TinySafeBoot on libavr in three size tiers