BlackMark
e4390d2ba8
The pin crosses libavr's phase 6 - the renamed system surface, the named serial configs, the receiver-tolerance table, the paged SPM receipts - and every loader image comes out size-identical: the full matrix on six representative chips (the exhaustive cross product on three of them), the stock and autobaud columns untouched, the four tsb tiers back on their recorded floors at 510/526/638/836. Byte parity was not free, and the two libavr defects it surfaced were fixed there rather than absorbed here. The EEPROM write procedure's step 2 - the SPMEN spin - had landed unconditionally and cost every build six bytes for a wait a polled loader can never take; it is scoped now, and the loaders state the datasheet's own omission clause (spm_interlock::omitted, DS40002061B 8.6.3). The blocking page erase/write grew an internal wait the tiers' settle() already provides, so the tiers issue the command form and pureboot keeps its host-driven sp_spm path. What the port states rather than inherits: the stock 115200 at 16 MHz sits +2.1 % past the receiver-tolerance table libavr now holds rates to, so the hardware links say .allow_baud_error = true - the same 2.5 % envelope pureboot_baud_feasible() has always enforced, proven on silicon across the fleet. rx_ready() reads readable() now. Alongside the pin: rule 33's ASCII sweep over every source (docs keep their typography), rule 34's InsertBraces in .clang-format with the tree reformatted, std::array over the simavr runners' raw buffers, and the stale Studio size in ide/README.md replaced by the claim its check-flags gate actually holds. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
72 lines
2.4 KiB
Python
72 lines
2.4 KiB
Python
#!/usr/bin/env python3
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"""--scan's walk and report logic, no simulator: the probe order, the rate
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arithmetic, and the advice's direction. The rate physics itself is not
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sim-testable - a pty carries bytes at any termios rate - so what the wire
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would arbitrate is pinned here as logic instead.
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Usage: test_scan.py <tool_py>
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"""
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import os
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import sys
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def fail(message):
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print(f"FAIL: {message}")
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sys.exit(1)
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def main():
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sys.path.insert(0, os.path.dirname(os.path.abspath(sys.argv[1])))
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import pureboot as pb
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walk = pb.scan_ratios()
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if walk != [0, -2, 2, -4, 4, -6, 6, -8, 8, -10, 10]:
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fail(f"probe walk is not built-rate-first, nearest-out: {walk}")
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if pb.scan_rate(9600, 4) != 9984 or pb.scan_rate(9600, -4) != 9216:
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fail("probe rate arithmetic")
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if pb.scan_rate(115200, 0) != 115200:
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fail("the built rate must probe unchanged")
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# A loader answering fast means a fast oscillator: the trim goes down.
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report = "\n".join(pb.scan_report(9600, 4, 6))
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for needle in ("9984", "+4 %", "--baud 9984", "4 steps lower", "pureboot 6"):
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if needle not in report:
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fail(f"+4 % report lacks {needle!r}:\n{report}")
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report = "\n".join(pb.scan_report(9600, -6, 6))
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if "6 steps higher" not in report:
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fail(f"-6 % report advises the wrong direction:\n{report}")
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report = "\n".join(pb.scan_report(9600, 0, 6))
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if "none" not in report or "steps" in report:
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fail(f"an on-rate answer must advise no trim:\n{report}")
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report = "\n".join(pb.scan_report(9600, 4, 6, clock=9600000))
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if "9984000" not in report:
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fail(f"the absolute clock must scale with the found ratio:\n{report}")
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# The walk's rates mostly have no termios B-constant, so the POSIX port
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# must set them through termios2 - probed on a pty, which accepts the
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# ioctl without caring about the speed. Without this every off-nominal
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# probe would abort the walk on the platform --scan matters most on.
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if os.name == "posix":
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import pty
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master, slave = pty.openpty()
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try:
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port = pb.Port(os.ttyname(slave), pb.scan_rate(9600, 4))
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port.set_baud(pb.scan_rate(9600, -4))
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port.close()
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except pb.Error as error:
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fail(f"PosixPort refused an off-nominal probe rate: {error}")
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finally:
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os.close(master)
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os.close(slave)
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print("OK")
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if __name__ == "__main__":
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main()
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