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docs: the one-wire section's sizes catch up with v9

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The v9 update moved the size table and the tightest-fit paragraph and
missed this section: the autobaud + OSCCAL twins measure 480 now, not
502, and the hardware half-duplex trio is 392/428/440. The claims
around the numbers were true all along - one-wire still measures the
same as two-wire, and the +42..50 delta over stock still holds exactly.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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BlackMark
2026-08-09 16:35:55 +02:00
parent e4390d2ba8
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pureboot/README.md
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@@ -147,14 +147,14 @@ Each backend has its shape:
an edge. This costs nothing: the frame's direction wrap is exactly what an edge. This costs nothing: the frame's direction wrap is exactly what
the dropped second-pin init paid, and the tightest image in the space — the dropped second-pin init paid, and the tightest image in the space —
the 1284s' autobaud + `OSCCAL` on their USART's RXD — measures the same the 1284s' autobaud + `OSCCAL` on their USART's RXD — measures the same
502 bytes one-wire as two-wire. On a USART's own pin the release applies 480 bytes one-wire as two-wire. On a USART's own pin the release applies
as ever, RXD included: `RXEN` forces that pin's direction (§20.7.3), as ever, RXD included: `RXEN` forces that pin's direction (§20.7.3),
which a receive-only link could live with and a driven shared pin cannot. which a receive-only link could live with and a driven shared pin cannot.
- **The hardware USART** (`SERIAL hardware`/`auto` + `HALF_DUPLEX`) uses - **The hardware USART** (`SERIAL hardware`/`auto` + `HALF_DUPLEX`) uses
libavr's `.half_duplex` turn-around — exactly one direction enabled at a libavr's `.half_duplex` turn-around — exactly one direction enabled at a
time, each written byte held to transmit-complete before the line can be time, each written byte held to transmit-complete before the line can be
released — and needs RXD and TXD tied together off-chip. It costs released — and needs RXD and TXD tied together off-chip. It costs
+42…50 B over the stock loader (m8 404, m328P 440, 1284P 460 — all far +42…50 B over the stock loader (m8 392, m328P 428, 1284P 440 — all far
inside the slot); the activation window is unchanged, its poll merely inside the slot); the activation window is unchanged, its poll merely
runs through the release-line test (18 cycles a poll in bit-addressable runs through the release-line test (18 cycles a poll in bit-addressable
I/O, 22 in extended — measured, and held per chip by I/O, 22 in extended — measured, and held per chip by