From b4243a89a3f46126a1846aaeff4257ab50e0b793 Mon Sep 17 00:00:00 2001 From: BlackMark Date: Sun, 9 Aug 2026 16:35:55 +0200 Subject: [PATCH] docs: the one-wire section's sizes catch up with v9 The v9 update moved the size table and the tightest-fit paragraph and missed this section: the autobaud + OSCCAL twins measure 480 now, not 502, and the hardware half-duplex trio is 392/428/440. The claims around the numbers were true all along - one-wire still measures the same as two-wire, and the +42..50 delta over stock still holds exactly. Co-Authored-By: Claude Fable 5 --- pureboot/README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pureboot/README.md b/pureboot/README.md index 083b8fe..dc725f3 100644 --- a/pureboot/README.md +++ b/pureboot/README.md @@ -147,14 +147,14 @@ Each backend has its shape: an edge. This costs nothing: the frame's direction wrap is exactly what the dropped second-pin init paid, and the tightest image in the space — the 1284s' autobaud + `OSCCAL` on their USART's RXD — measures the same - 502 bytes one-wire as two-wire. On a USART's own pin the release applies + 480 bytes one-wire as two-wire. On a USART's own pin the release applies as ever, RXD included: `RXEN` forces that pin's direction (§20.7.3), which a receive-only link could live with and a driven shared pin cannot. - **The hardware USART** (`SERIAL hardware`/`auto` + `HALF_DUPLEX`) uses libavr's `.half_duplex` turn-around — exactly one direction enabled at a time, each written byte held to transmit-complete before the line can be released — and needs RXD and TXD tied together off-chip. It costs - +42…50 B over the stock loader (m8 404, m328P 440, 1284P 460 — all far + +42…50 B over the stock loader (m8 392, m328P 428, 1284P 440 — all far inside the slot); the activation window is unchanged, its poll merely runs through the release-line test (18 cycles a poll in bit-addressable I/O, 22 in extended — measured, and held per chip by