tsb: document the three tiers at full parity in the build file

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
2026-07-19 16:50:18 +02:00
parent beff7bb3ee
commit ac9447c07f

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@@ -45,9 +45,13 @@ endif()
# loader has no use for the crt or the vector table. The naked entry sits in
# .vectors, laid first, and runs. The boot base is FLASHEND+1 minus the section
# size; the linker section-start and the source's boot_bytes agree.
# tsb_asm — inline-asm variant, the headline: ≤512 B, the 512 B section.
# tsb_pure / tsb_tricks — pure-C++ and compiler-trickery variants, larger,
# shown in the 1 KB section (BOOTSZ=10) they fit.
# All three implement the full oracle feature set (see oracle/README.md):
# watchdog bail, one-wire half-duplex, config-page activation timeout, password
# gate, emergency erase, config/flash/EEPROM read-write. They differ only in how.
# tsb_asm — minimal inline asm, the headline: 502 B in the 512 B section,
# matching the hand-written oracle's size and features.
# tsb_tricks — compiler trickery, no asm: 808 B in the 1 KB section (BOOTSZ=10).
# tsb_pure — pure idiomatic libavr: 950 B in the 1 KB section.
#
# add_tsb_variant(<name> <boot-section-bytes>)
function(add_tsb_variant name bytes)