test: the exhaustive clock x baud x backend size matrix
Every plausible oscillator against every rate it reaches against every backend, on one chip per size-bearing class, under --full only. The baud ladder becomes a reachability predicate the enumeration filters on, so an unreachable point drops out instead of aborting the configure. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
@@ -233,11 +233,11 @@ if(PROJECT_IS_TOP_LEVEL)
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# The size matrix: every configuration axis that could move the image
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# size — the serial backend (different code), the USART instance
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# (different registers), the clock (different constants), and the baud
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# through the two shapes its bit timing takes — each combination must
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# still fit the chip's slot budget. Pins are size-neutral (port and bit
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# are immediate operands) and the timeout is a constant, so neither adds
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# an axis. The stock build is one point of this matrix and already has
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# its test.
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# through the shapes its bit timing takes — each combination must still
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# fit the chip's slot budget. Pins are size-neutral (port and bit are
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# immediate operands) and the timeout is a constant, so neither adds an
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# axis. The stock build is one point of this matrix and already has its
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# test.
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function(pureboot_size_variant name)
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pureboot_add_loader(${name} ${ARGN})
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add_test(NAME ${name}.size
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@@ -245,14 +245,67 @@ if(PROJECT_IS_TOP_LEVEL)
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-DLIMIT=${PUREBOOT_LIMIT} -P ${CMAKE_CURRENT_SOURCE_DIR}/test/check_size.cmake)
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endfunction()
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# One point of the exhaustive matrix, named from its resolved parameters
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# so the enumeration cannot collide with itself. Unreachable rates drop
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# out here rather than aborting the configure.
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function(pureboot_matrix_point hz baud link)
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if(link STREQUAL "software")
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pureboot_baud_feasible(${hz} ${baud} 1 _ok)
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set(_args SERIAL software)
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else()
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pureboot_baud_feasible(${hz} ${baud} 0 _ok)
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set(_args USART ${link})
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endif()
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if(_ok)
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pureboot_size_variant(pbm_${hz}_${baud}_${link} CLOCK ${hz} BAUD ${baud} ${_args})
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endif()
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endfunction()
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# Clock points: the shipped-fuse floor (CKDIV8), the calibrated RC, and
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# the crystal the stock build assumes (the tiny13's ladder is its own RC
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# menu — it has no crystal option).
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if(LIBAVR_MCU MATCHES "^attiny13")
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set(_matrix_clocks 1200000 4800000 9600000)
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set(_full_clocks 128000 600000 1200000 4800000 9600000)
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else()
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set(_matrix_clocks 1000000 8000000 16000000)
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set(_full_clocks 128000 1000000 1843200 2000000 3686400 4000000 7372800 8000000
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11059200 12000000 14745600 16000000 18432000 20000000)
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endif()
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# The exhaustive cross product: every clock a deployment plausibly runs
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# — the internal oscillators, the shipped CKDIV8 floor, the plain
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# crystals and the UART crystals — against every rate, against every
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# backend. Beyond the ladder the list carries the slow rates a
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# sub-megahertz oscillator is left with, which no ladder rate reaches
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# (16000 Bd is the only rate the 128 kHz oscillator holds exactly); at
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# the fast clocks those same rates also select the software UART's
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# 16-bit _delay_loop_2 bit spin (two words more setup at each of its five
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# sites), the largest image the space produces and a shape the ladder
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# default — always the *fastest* rate a clock reaches — never picks.
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#
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# Bounded to one chip per size-bearing class: flash addressing (the
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# word-addressed 1284), hand-over shape (the patched vector on the tinies
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# and m48s), page size, and USART inventory. Everything else in the image
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# is chip-independent code, so a further chip buys builds and no
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# coverage; every chip outside the set carries the compact matrix.
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get_property(_full_bauds GLOBAL PROPERTY PUREBOOT_BAUD_LADDER)
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list(APPEND _full_bauds 16000 4800 2400 1200)
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set(_matrix_spot attiny13a attiny85 atmega48pa atmega8a atmega168pa
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atmega328p atmega164a atmega644a atmega1284p)
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if(DEFINED ENV{PUREBOOT_FULL_MATRIX} AND LIBAVR_MCU IN_LIST _matrix_spot)
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foreach(_matrix_hz IN LISTS _full_clocks)
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foreach(_matrix_baud IN LISTS _full_bauds)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} software)
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if(PUREBOOT_HAS_USART)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 0)
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endif()
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if(PUREBOOT_HAS_USART1)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 1)
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endif()
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endforeach()
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endforeach()
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else()
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foreach(_matrix_hz IN LISTS _matrix_clocks)
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math(EXPR _matrix_khz "${_matrix_hz} / 1000")
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if(PUREBOOT_HAS_USART OR NOT _matrix_hz EQUAL _pb_stock_hz)
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@@ -265,22 +318,13 @@ if(PROJECT_IS_TOP_LEVEL)
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pureboot_size_variant(pureboot_usart1_${_matrix_khz}k CLOCK ${_matrix_hz} USART 1)
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endif()
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endforeach()
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list(GET _matrix_clocks -1 _matrix_top_hz)
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pureboot_size_variant(pureboot_sw_wide CLOCK ${_matrix_top_hz} BAUD 9600 SERIAL software)
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endif()
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if(PUREBOOT_HAS_USART1)
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pureboot_size_variant(pureboot_usart1 USART 1)
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endif()
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# The baud axis, whose one size-bearing shape the ladder never picks: a
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# software UART spins out each bit with _delay_loop_1 while the count
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# fits a byte and with the 16-bit _delay_loop_2 beyond it, two words more
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# setup at every one of its five sites — the largest image the
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# configuration space produces. The ladder default takes the *fastest*
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# rate a clock reaches, which always lands in the byte, so the wide form
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# needs the slowest ladder rate against the fastest clock to appear. The
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# hardware USART has no such shape: its baud is a divisor constant, and
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# the ladder's U2X solutions are already its larger form.
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list(GET _matrix_clocks -1 _matrix_top_hz)
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pureboot_size_variant(pureboot_sw_wide CLOCK ${_matrix_top_hz} BAUD 9600 SERIAL software)
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# One configured deployment end to end — a real board's shape rather
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# than the stock assumption: the ATmega328P on its shipped 1 MHz fuses,
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# the software UART on hand-picked pins (TX = PB1, RX = PB5), the ladder
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@@ -146,16 +146,19 @@ set(PUREBOOT_HAS_USART ${_pb_has_usart} PARENT_SCOPE)
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set(PUREBOOT_HAS_USART1 ${_pb_has_usart1} PARENT_SCOPE)
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set(PUREBOOT_SIM_MCU ${_pb_sim_mcu} PARENT_SCOPE)
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# The fastest standard rate the clock reaches within 2.5 %, by the same
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# best-of-U2X-and-plain divisor search libavr's solve_baud runs, so a default
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# The rates a default may pick, fastest first.
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set_property(GLOBAL PROPERTY PUREBOOT_BAUD_LADDER 115200 57600 38400 19200 9600)
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# Whether <baud> is reachable from <clock> within 2.5 %, by the same
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# best-of-U2X-and-plain divisor search libavr's solve_baud runs, so a build
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# never trips the compile-time error it is checked against. A software build
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# also needs the polled receiver's 100-cycles-a-bit floor: at low clocks the
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# U2X divisor reaches rates the bit-banged sampler cannot.
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function(pureboot_default_baud clock software outvar)
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foreach(baud 115200 57600 38400 19200 9600)
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function(pureboot_baud_feasible clock baud software outvar)
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set(${outvar} 0 PARENT_SCOPE)
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math(EXPR _cycles "${clock} / ${baud}")
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if(software AND _cycles LESS 100)
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continue()
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return()
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endif()
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foreach(divisor 8 16)
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math(EXPR _step "${divisor} * ${baud}")
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@@ -170,12 +173,24 @@ function(pureboot_default_baud clock software outvar)
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endif()
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math(EXPR _error_bp "${_delta} * 10000 / ${baud}")
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if(_error_bp LESS_EQUAL 250)
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set(${outvar} 1 PARENT_SCOPE)
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return()
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endif()
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endforeach()
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endfunction()
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# The fastest ladder rate the clock reaches.
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function(pureboot_default_baud clock software outvar)
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get_property(_ladder GLOBAL PROPERTY PUREBOOT_BAUD_LADDER)
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foreach(baud ${_ladder})
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pureboot_baud_feasible(${clock} ${baud} ${software} _ok)
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if(_ok)
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set(${outvar} ${baud} PARENT_SCOPE)
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return()
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endif()
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endforeach()
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endforeach()
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message(FATAL_ERROR "pureboot: no standard baud rate fits a ${clock} Hz clock within 2.5 %")
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message(FATAL_ERROR "pureboot: no standard baud rate fits a ${clock} Hz clock within 2.5 % "
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"— pass BAUD <rate> to deploy a non-standard one")
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endfunction()
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# pureboot_add_loader(<name> [CLOCK <hz>] [BAUD <bd>]
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@@ -309,6 +309,13 @@ Per chip preset, `ctest` runs:
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the configuration space produces, and a shape the ladder default (always the
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*fastest* rate a clock reaches) never picks. Pins are immediate operands and
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the timeout is a constant: neither is an axis;
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- `pbm_*.size` — under `--full`, the exhaustive cross product replacing that
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compact matrix: every plausible oscillator (the internal ones, the CKDIV8
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floor, the plain and the UART crystals) × every rate reachable from it ×
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every backend, unreachable combinations dropping out rather than aborting
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the configure. Bounded to one chip per size-bearing class — flash
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addressing, hand-over shape, page size, USART inventory — since everything
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else in the image is chip-independent code;
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- `pureboot.pi` — the position-independence lint: no absolute `jmp`/`call`, the
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info block within the image's first 256 bytes;
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- `pureboot.planner` — the host tool's pure logic: programming orders and their
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@@ -2,12 +2,14 @@
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# The port's gate: every chip's generated workflow — build, size matrix, and
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# the simulator-driven protocol suites. --full adds the reflect-spot builds
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# (libavr's rule: reflect compiles are bounded to its spot set, never the
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# full matrix). LIBAVR_ROOT must point at the libavr checkout.
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# full matrix) and swaps the compact size matrix for the exhaustive
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# clock × baud × backend cross product. LIBAVR_ROOT must point at the libavr
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# checkout.
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set -e
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cd "$(dirname "$0")/.."
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full=0
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[[ "$1" == "--full" ]] && { full=1; shift; }
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[[ "$1" == "--full" ]] && { full=1; shift; export PUREBOOT_FULL_MATRIX=1; }
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CHIPS=(attiny13 attiny13a attiny25 attiny45 attiny85
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atmega8 atmega8a atmega16 atmega16a atmega32 atmega32a
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