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Added enums for register bit positions

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This commit is contained in:
BlackMark 2019-07-30 20:56:16 +02:00
parent 65bbf5e96a
commit fbd087808a
1 changed files with 44 additions and 11 deletions
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55
hardware0.hpp
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@ -32,6 +32,39 @@ struct Registers0 {
static constexpr volatile auto *BAUD_REG_H = &UBRR0H; static constexpr volatile auto *BAUD_REG_H = &UBRR0H;
}; };
enum ControlFlagsA {
MULTI_PROC_COMM_MODE = MPCM0,
SPEED_2X = U2X0,
PARITY_ERROR = UPE0,
DATA_OVER_RUN = DOR0,
FRAME_ERROR = FE0,
DATA_REG_EMPTY = UDRE0,
TRANSMIT_COMPLETE = TXC0,
RECEIVE_COMPLETE = RXC0,
};
enum ControlFlagsB {
TX_DATA_BIT_8 = TXB80,
RX_DATA_BIT_8 = RXB80,
CHAR_SIZE_2 = UCSZ02,
TX_ENABLE = TXEN0,
RX_ENABLE = RXEN0,
DATA_REG_EMPTY_INT_ENABLE = UDRIE0,
TX_INT_ENABLE = TXCIE0,
RX_INT_ENABLE = RXCIE0,
};
enum ControlFlagsC {
CLK_POLARITY = UCPOL0,
CHAR_SIZE_0 = UCSZ00,
CHAR_SIZE_1 = UCSZ01,
STOP_BIT_SEL = USBS0,
PARITY_MODE_0 = UPM00,
PARITY_MODE_1 = UPM01,
MODE_SEL_0 = UMSEL00,
MODE_SEL_1 = UMSEL01,
};
static constexpr auto getLastRxError() {} static constexpr auto getLastRxError() {}
static constexpr void set2xSpeed() {} static constexpr void set2xSpeed() {}
@ -116,17 +149,17 @@ class Hardware0 {
dataBitsVal.regCVal = 0; dataBitsVal.regCVal = 0;
break; break;
case DataBits::SIX: case DataBits::SIX:
dataBitsVal.regCVal = (1 << UCSZ00); dataBitsVal.regCVal = (1 << detail::CHAR_SIZE_0);
break; break;
case DataBits::SEVEN: case DataBits::SEVEN:
dataBitsVal.regCVal = (1 << UCSZ01); dataBitsVal.regCVal = (1 << detail::CHAR_SIZE_1);
break; break;
case DataBits::EIGHT: case DataBits::EIGHT:
dataBitsVal.regCVal = (1 << UCSZ01) | (1 << UCSZ00); dataBitsVal.regCVal = (1 << detail::CHAR_SIZE_1) | (1 << detail::CHAR_SIZE_0);
break; break;
case DataBits::NINE: case DataBits::NINE:
dataBitsVal.regCVal = (1 << UCSZ01) | (1 << UCSZ00); dataBitsVal.regCVal = (1 << detail::CHAR_SIZE_1) | (1 << detail::CHAR_SIZE_0);
dataBitsVal.regBVal = (1 << UCSZ02); dataBitsVal.regBVal = (1 << detail::CHAR_SIZE_2);
break; break;
} }
@ -138,9 +171,9 @@ class Hardware0 {
uint8_t parityVal = 0; uint8_t parityVal = 0;
if (PARITY == Parity::EVEN) if (PARITY == Parity::EVEN)
parityVal = (1 << UPM01); parityVal = (1 << detail::PARITY_MODE_1);
else if (PARITY == Parity::ODD) else if (PARITY == Parity::ODD)
parityVal = (1 << UPM01) | (1 << UPM00); parityVal = (1 << detail::PARITY_MODE_1) | (1 << detail::PARITY_MODE_0);
return parityVal; return parityVal;
} }
@ -150,7 +183,7 @@ class Hardware0 {
uint8_t stopBitsVal = 0; uint8_t stopBitsVal = 0;
if (STOP_BITS == StopBits::TWO) if (STOP_BITS == StopBits::TWO)
stopBitsVal = (1 << USBS0); stopBitsVal = (1 << detail::STOP_BIT_SEL);
return stopBitsVal; return stopBitsVal;
} }
@ -162,7 +195,7 @@ class Hardware0 {
uint8_t modeVal = 0; uint8_t modeVal = 0;
if (mode == Mode::SYNCHRONOUS_MASTER || mode == Mode::SYNCHRONOUS_SLAVE) { if (mode == Mode::SYNCHRONOUS_MASTER || mode == Mode::SYNCHRONOUS_SLAVE) {
modeVal = (1 << UMSEL00); modeVal = (1 << detail::MODE_SEL_0);
} }
return modeVal; return modeVal;
@ -174,7 +207,7 @@ class Hardware0 {
uint8_t enableVal = 0; uint8_t enableVal = 0;
if (enable) if (enable)
enableVal = (1 << RXEN0); enableVal = (1 << detail::RX_ENABLE);
return enableVal; return enableVal;
} }
@ -185,7 +218,7 @@ class Hardware0 {
uint8_t enableVal = 0; uint8_t enableVal = 0;
if (enable) if (enable)
enableVal = (1 << TXEN0); enableVal = (1 << detail::TX_ENABLE);
return enableVal; return enableVal;
} }