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uart.cpp
714
uart.cpp
@ -36,306 +36,304 @@ LICENSE:
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GNU General Public License for more details.
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*************************************************************************/
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <avr/pgmspace.h>
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#include "uart.h"
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#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <avr/pgmspace.h>
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/*
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* constants and macros
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*/
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/* size of RX/TX buffers */
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#define UART_RX_BUFFER_MASK ( UART_RX_BUFFER_SIZE - 1)
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#define UART_TX_BUFFER_MASK ( UART_TX_BUFFER_SIZE - 1)
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#define UART_RX_BUFFER_MASK (UART_RX_BUFFER_SIZE - 1)
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#define UART_TX_BUFFER_MASK (UART_TX_BUFFER_SIZE - 1)
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#if ( UART_RX_BUFFER_SIZE & UART_RX_BUFFER_MASK )
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#if (UART_RX_BUFFER_SIZE & UART_RX_BUFFER_MASK)
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#error RX buffer size is not a power of 2
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#endif
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#if ( UART_TX_BUFFER_SIZE & UART_TX_BUFFER_MASK )
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#if (UART_TX_BUFFER_SIZE & UART_TX_BUFFER_MASK)
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#error TX buffer size is not a power of 2
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#endif
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#if defined(__AVR_AT90S2313__) || defined(__AVR_AT90S4414__) || defined(__AVR_AT90S8515__) || \
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defined(__AVR_AT90S4434__) || defined(__AVR_AT90S8535__) || \
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defined(__AVR_ATmega103__)
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/* old AVR classic or ATmega103 with one UART */
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#define UART0_RECEIVE_INTERRUPT UART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect
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#define UART0_STATUS USR
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#define UART0_CONTROL UCR
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRR
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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defined(__AVR_AT90S4434__) || defined(__AVR_AT90S8535__) || defined(__AVR_ATmega103__)
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/* old AVR classic or ATmega103 with one UART */
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#define UART0_RECEIVE_INTERRUPT UART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect
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#define UART0_STATUS USR
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#define UART0_CONTROL UCR
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRR
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#elif defined(__AVR_AT90S2333__) || defined(__AVR_AT90S4433__)
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/* old AVR classic with one UART */
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#define UART0_RECEIVE_INTERRUPT UART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRR
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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/* old AVR classic with one UART */
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#define UART0_RECEIVE_INTERRUPT UART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRR
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#elif defined(__AVR_AT90PWM216__) || defined(__AVR_AT90PWM316__)
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/* AT90PWN216/316 with one USART */
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#define UART0_RECEIVE_INTERRUPT USART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_CONTROLC UCSRC
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRRL
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#define UART0_UBRRH UBRRH
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#define UART0_BIT_UCSZ0 UCSZ0
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#define UART0_BIT_UCSZ1 UCSZ1
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#elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega8A__) || \
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defined(__AVR_ATmega16__) || defined(__AVR_ATmega16A__) || \
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defined(__AVR_ATmega32__) || defined(__AVR_ATmega32A__) || \
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/* AT90PWN216/316 with one USART */
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#define UART0_RECEIVE_INTERRUPT USART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_CONTROLC UCSRC
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRRL
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#define UART0_UBRRH UBRRH
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#define UART0_BIT_UCSZ0 UCSZ0
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#define UART0_BIT_UCSZ1 UCSZ1
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#elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega8A__) || defined(__AVR_ATmega16__) || \
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defined(__AVR_ATmega16A__) || defined(__AVR_ATmega32__) || defined(__AVR_ATmega32A__) || \
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defined(__AVR_ATmega323__)
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/* ATmega with one USART */
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#define UART0_RECEIVE_INTERRUPT USART_RXC_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_CONTROLC UCSRC
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRRL
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#define UART0_UBRRH UBRRH
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#define UART0_BIT_UCSZ0 UCSZ0
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#define UART0_BIT_UCSZ1 UCSZ1
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#define UART0_BIT_URSEL URSEL
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#elif defined (__AVR_ATmega8515__) || defined(__AVR_ATmega8535__)
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#define UART0_RECEIVE_INTERRUPT USART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_CONTROLC UCSRC
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRRL
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#define UART0_UBRRH UBRRH
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#define UART0_BIT_UCSZ0 UCSZ0
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#define UART0_BIT_UCSZ1 UCSZ1
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#define UART0_BIT_URSEL URSEL
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/* ATmega with one USART */
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#define UART0_RECEIVE_INTERRUPT USART_RXC_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_CONTROLC UCSRC
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRRL
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#define UART0_UBRRH UBRRH
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#define UART0_BIT_UCSZ0 UCSZ0
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#define UART0_BIT_UCSZ1 UCSZ1
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#define UART0_BIT_URSEL URSEL
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#elif defined(__AVR_ATmega8515__) || defined(__AVR_ATmega8535__)
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#define UART0_RECEIVE_INTERRUPT USART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_CONTROLC UCSRC
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRRL
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#define UART0_UBRRH UBRRH
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#define UART0_BIT_UCSZ0 UCSZ0
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#define UART0_BIT_UCSZ1 UCSZ1
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#define UART0_BIT_URSEL URSEL
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#elif defined(__AVR_ATmega163__)
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/* ATmega163 with one UART */
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#define UART0_RECEIVE_INTERRUPT UART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRR
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#define UART0_UBRRH UBRRHI
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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/* ATmega163 with one UART */
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#define UART0_RECEIVE_INTERRUPT UART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRR
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#define UART0_UBRRH UBRRHI
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#elif defined(__AVR_ATmega162__)
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/* ATmega with two USART */
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#define ATMEGA_USART1
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#define UART0_RECEIVE_INTERRUPT USART0_RXC_vect
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#define UART1_RECEIVE_INTERRUPT USART1_RXC_vect
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#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
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#define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect
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#define UART0_STATUS UCSR0A
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#define UART0_CONTROL UCSR0B
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#define UART0_CONTROLC UCSR0C
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#define UART0_DATA UDR0
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#define UART0_UDRIE UDRIE0
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#define UART0_UBRRL UBRR0L
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#define UART0_UBRRH UBRR0H
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#define UART0_BIT_URSEL URSEL0
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#define UART0_BIT_U2X U2X0
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#define UART0_BIT_RXCIE RXCIE0
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#define UART0_BIT_RXEN RXEN0
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#define UART0_BIT_TXEN TXEN0
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#define UART0_BIT_UCSZ0 UCSZ00
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#define UART0_BIT_UCSZ1 UCSZ01
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#define UART1_STATUS UCSR1A
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#define UART1_CONTROL UCSR1B
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#define UART1_CONTROLC UCSR1C
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#define UART1_DATA UDR1
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#define UART1_UDRIE UDRIE1
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#define UART1_UBRRL UBRR1L
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#define UART1_UBRRH UBRR1H
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#define UART1_BIT_URSEL URSEL1
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#define UART1_BIT_U2X U2X1
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#define UART1_BIT_RXCIE RXCIE1
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#define UART1_BIT_RXEN RXEN1
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#define UART1_BIT_TXEN TXEN1
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#define UART1_BIT_UCSZ0 UCSZ10
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#define UART1_BIT_UCSZ1 UCSZ11
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/* ATmega with two USART */
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#define ATMEGA_USART1
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#define UART0_RECEIVE_INTERRUPT USART0_RXC_vect
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#define UART1_RECEIVE_INTERRUPT USART1_RXC_vect
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#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
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#define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect
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#define UART0_STATUS UCSR0A
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#define UART0_CONTROL UCSR0B
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#define UART0_CONTROLC UCSR0C
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#define UART0_DATA UDR0
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#define UART0_UDRIE UDRIE0
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#define UART0_UBRRL UBRR0L
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#define UART0_UBRRH UBRR0H
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#define UART0_BIT_URSEL URSEL0
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#define UART0_BIT_U2X U2X0
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#define UART0_BIT_RXCIE RXCIE0
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#define UART0_BIT_RXEN RXEN0
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#define UART0_BIT_TXEN TXEN0
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#define UART0_BIT_UCSZ0 UCSZ00
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#define UART0_BIT_UCSZ1 UCSZ01
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#define UART1_STATUS UCSR1A
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#define UART1_CONTROL UCSR1B
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#define UART1_CONTROLC UCSR1C
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#define UART1_DATA UDR1
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#define UART1_UDRIE UDRIE1
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#define UART1_UBRRL UBRR1L
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#define UART1_UBRRH UBRR1H
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#define UART1_BIT_URSEL URSEL1
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#define UART1_BIT_U2X U2X1
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#define UART1_BIT_RXCIE RXCIE1
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#define UART1_BIT_RXEN RXEN1
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#define UART1_BIT_TXEN TXEN1
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#define UART1_BIT_UCSZ0 UCSZ10
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#define UART1_BIT_UCSZ1 UCSZ11
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#elif defined(__AVR_ATmega161__)
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/* ATmega with UART */
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#error "AVR ATmega161 currently not supported by this libaray !"
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/* ATmega with UART */
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#error "AVR ATmega161 currently not supported by this libaray !"
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#elif defined(__AVR_ATmega169__)
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/* ATmega with one USART */
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#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_CONTROLC UCSRC
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRRL
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#define UART0_UBRRH UBRRH
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#define UART0_BIT_UCSZ0 UCSZ0
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#define UART0_BIT_UCSZ1 UCSZ1
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#elif defined(__AVR_ATmega48__) || defined(__AVR_ATmega48A__) || defined(__AVR_ATmega48P__) || defined(__AVR_ATmega48PA__) || defined(__AVR_ATmega48PB__) || \
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defined(__AVR_ATmega88__) || defined(__AVR_ATmega88A__) || defined(__AVR_ATmega88P__) || defined(__AVR_ATmega88PA__) || defined(__AVR_ATmega88PB__) || \
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defined(__AVR_ATmega168__) || defined(__AVR_ATmega168A__)|| defined(__AVR_ATmega168P__)|| defined(__AVR_ATmega168PA__) || defined(__AVR_ATmega168PB__) || \
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defined(__AVR_ATmega328__) || defined(__AVR_ATmega328P__) || \
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defined(__AVR_ATmega3250__) || defined(__AVR_ATmega3290__) ||defined(__AVR_ATmega6450__) || defined(__AVR_ATmega6490__)
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/* ATmega with one USART */
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#define UART0_RECEIVE_INTERRUPT USART_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
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#define UART0_STATUS UCSR0A
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#define UART0_CONTROL UCSR0B
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#define UART0_CONTROLC UCSR0C
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#define UART0_DATA UDR0
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#define UART0_UDRIE UDRIE0
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#define UART0_UBRRL UBRR0L
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#define UART0_UBRRH UBRR0H
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#define UART0_BIT_U2X U2X0
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#define UART0_BIT_RXCIE RXCIE0
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#define UART0_BIT_RXEN RXEN0
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#define UART0_BIT_TXEN TXEN0
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#define UART0_BIT_UCSZ0 UCSZ00
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#define UART0_BIT_UCSZ1 UCSZ01
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/* ATmega with one USART */
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#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
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#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
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#define UART0_STATUS UCSRA
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#define UART0_CONTROL UCSRB
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#define UART0_CONTROLC UCSRC
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#define UART0_DATA UDR
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#define UART0_UDRIE UDRIE
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#define UART0_UBRRL UBRRL
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#define UART0_UBRRH UBRRH
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#define UART0_BIT_U2X U2X
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#define UART0_BIT_RXCIE RXCIE
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#define UART0_BIT_RXEN RXEN
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#define UART0_BIT_TXEN TXEN
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#define UART0_BIT_UCSZ0 UCSZ0
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#define UART0_BIT_UCSZ1 UCSZ1
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#elif defined(__AVR_ATmega48__) || defined(__AVR_ATmega48A__) || defined(__AVR_ATmega48P__) || \
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defined(__AVR_ATmega48PA__) || defined(__AVR_ATmega48PB__) || defined(__AVR_ATmega88__) || \
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defined(__AVR_ATmega88A__) || defined(__AVR_ATmega88P__) || defined(__AVR_ATmega88PA__) || \
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defined(__AVR_ATmega88PB__) || defined(__AVR_ATmega168__) || defined(__AVR_ATmega168A__) || \
|
||||
defined(__AVR_ATmega168P__) || defined(__AVR_ATmega168PA__) || defined(__AVR_ATmega168PB__) || \
|
||||
defined(__AVR_ATmega328__) || defined(__AVR_ATmega328P__) || defined(__AVR_ATmega3250__) || \
|
||||
defined(__AVR_ATmega3290__) || defined(__AVR_ATmega6450__) || defined(__AVR_ATmega6490__)
|
||||
/* ATmega with one USART */
|
||||
#define UART0_RECEIVE_INTERRUPT USART_RX_vect
|
||||
#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
|
||||
#define UART0_STATUS UCSR0A
|
||||
#define UART0_CONTROL UCSR0B
|
||||
#define UART0_CONTROLC UCSR0C
|
||||
#define UART0_DATA UDR0
|
||||
#define UART0_UDRIE UDRIE0
|
||||
#define UART0_UBRRL UBRR0L
|
||||
#define UART0_UBRRH UBRR0H
|
||||
#define UART0_BIT_U2X U2X0
|
||||
#define UART0_BIT_RXCIE RXCIE0
|
||||
#define UART0_BIT_RXEN RXEN0
|
||||
#define UART0_BIT_TXEN TXEN0
|
||||
#define UART0_BIT_UCSZ0 UCSZ00
|
||||
#define UART0_BIT_UCSZ1 UCSZ01
|
||||
#elif defined(__AVR_ATtiny2313__) || defined(__AVR_ATtiny2313A__) || defined(__AVR_ATtiny4313__)
|
||||
/* ATtiny with one USART */
|
||||
#define UART0_RECEIVE_INTERRUPT USART_RX_vect
|
||||
#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
|
||||
#define UART0_STATUS UCSRA
|
||||
#define UART0_CONTROL UCSRB
|
||||
#define UART0_CONTROLC UCSRC
|
||||
#define UART0_DATA UDR
|
||||
#define UART0_UDRIE UDRIE
|
||||
#define UART0_UBRRL UBRRL
|
||||
#define UART0_UBRRH UBRRH
|
||||
#define UART0_BIT_U2X U2X
|
||||
#define UART0_BIT_RXCIE RXCIE
|
||||
#define UART0_BIT_RXEN RXEN
|
||||
#define UART0_BIT_TXEN TXEN
|
||||
#define UART0_BIT_UCSZ0 UCSZ0
|
||||
#define UART0_BIT_UCSZ1 UCSZ1
|
||||
#elif defined(__AVR_ATmega329__) || defined(__AVR_ATmega649__) || defined(__AVR_ATmega3290__) || defined(__AVR_ATmega6490__) ||\
|
||||
defined(__AVR_ATmega169A__) || defined(__AVR_ATmega169PA__) || \
|
||||
defined(__AVR_ATmega329A__) || defined(__AVR_ATmega329PA__) || defined(__AVR_ATmega3290A__) || defined(__AVR_ATmega3290PA__) || \
|
||||
defined(__AVR_ATmega649A__) || defined(__AVR_ATmega649P__) || defined(__AVR_ATmega6490A__) || defined(__AVR_ATmega6490P__) || \
|
||||
defined(__AVR_ATmega165__) || defined(__AVR_ATmega325__) || defined(__AVR_ATmega645__) || defined(__AVR_ATmega3250__) || defined(__AVR_ATmega6450__) || \
|
||||
defined(__AVR_ATmega165A__) || defined(__AVR_ATmega165PA__) || \
|
||||
defined(__AVR_ATmega325A__) || defined(__AVR_ATmega325PA__) || defined(__AVR_ATmega3250A__) || defined(__AVR_ATmega3250PA__) ||\
|
||||
defined(__AVR_ATmega645A__) || defined(__AVR_ATmega645PA__) || defined(__AVR_ATmega6450A__) || defined(__AVR_ATmega6450PA__) || \
|
||||
defined(__AVR_ATmega644__)
|
||||
/* ATmega with one USART */
|
||||
#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
|
||||
#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
|
||||
#define UART0_STATUS UCSR0A
|
||||
#define UART0_CONTROL UCSR0B
|
||||
#define UART0_CONTROLC UCSR0C
|
||||
#define UART0_DATA UDR0
|
||||
#define UART0_UDRIE UDRIE0
|
||||
#define UART0_UBRRL UBRR0L
|
||||
#define UART0_UBRRH UBRR0H
|
||||
#define UART0_BIT_U2X U2X0
|
||||
#define UART0_BIT_RXCIE RXCIE0
|
||||
#define UART0_BIT_RXEN RXEN0
|
||||
#define UART0_BIT_TXEN TXEN0
|
||||
#define UART0_BIT_UCSZ0 UCSZ00
|
||||
#define UART0_BIT_UCSZ1 UCSZ01
|
||||
#elif defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__) || defined(__AVR_ATmega128A__) ||\
|
||||
defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__) || \
|
||||
defined(__AVR_ATmega164P__) || defined(__AVR_ATmega324P__) || defined(__AVR_ATmega644P__) || \
|
||||
defined(__AVR_ATmega164A__) || defined(__AVR_ATmega164PA__) || defined(__AVR_ATmega324A__) || defined(__AVR_ATmega324PA__) || \
|
||||
defined(__AVR_ATmega644A__) || defined(__AVR_ATmega644PA__) || defined(__AVR_ATmega1284__) || defined(__AVR_ATmega1284P__) ||\
|
||||
defined(__AVR_ATtiny1634__)
|
||||
/* ATmega with two USART */
|
||||
#define ATMEGA_USART1
|
||||
#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
|
||||
#define UART1_RECEIVE_INTERRUPT USART1_RX_vect
|
||||
#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
|
||||
#define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect
|
||||
#define UART0_STATUS UCSR0A
|
||||
#define UART0_CONTROL UCSR0B
|
||||
#define UART0_CONTROLC UCSR0C
|
||||
#define UART0_DATA UDR0
|
||||
#define UART0_UDRIE UDRIE0
|
||||
#define UART0_UBRRL UBRR0L
|
||||
#define UART0_UBRRH UBRR0H
|
||||
#define UART0_BIT_U2X U2X0
|
||||
#define UART0_BIT_RXCIE RXCIE0
|
||||
#define UART0_BIT_RXEN RXEN0
|
||||
#define UART0_BIT_TXEN TXEN0
|
||||
#define UART0_BIT_UCSZ0 UCSZ00
|
||||
#define UART0_BIT_UCSZ1 UCSZ01
|
||||
#define UART1_STATUS UCSR1A
|
||||
#define UART1_CONTROL UCSR1B
|
||||
#define UART1_CONTROLC UCSR1C
|
||||
#define UART1_DATA UDR1
|
||||
#define UART1_UDRIE UDRIE1
|
||||
#define UART1_UBRRL UBRR1L
|
||||
#define UART1_UBRRH UBRR1H
|
||||
#define UART1_BIT_U2X U2X1
|
||||
#define UART1_BIT_RXCIE RXCIE1
|
||||
#define UART1_BIT_RXEN RXEN1
|
||||
#define UART1_BIT_TXEN TXEN1
|
||||
#define UART1_BIT_UCSZ0 UCSZ10
|
||||
#define UART1_BIT_UCSZ1 UCSZ11
|
||||
/* ATtiny with one USART */
|
||||
#define UART0_RECEIVE_INTERRUPT USART_RX_vect
|
||||
#define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect
|
||||
#define UART0_STATUS UCSRA
|
||||
#define UART0_CONTROL UCSRB
|
||||
#define UART0_CONTROLC UCSRC
|
||||
#define UART0_DATA UDR
|
||||
#define UART0_UDRIE UDRIE
|
||||
#define UART0_UBRRL UBRRL
|
||||
#define UART0_UBRRH UBRRH
|
||||
#define UART0_BIT_U2X U2X
|
||||
#define UART0_BIT_RXCIE RXCIE
|
||||
#define UART0_BIT_RXEN RXEN
|
||||
#define UART0_BIT_TXEN TXEN
|
||||
#define UART0_BIT_UCSZ0 UCSZ0
|
||||
#define UART0_BIT_UCSZ1 UCSZ1
|
||||
#elif defined(__AVR_ATmega329__) || defined(__AVR_ATmega649__) || defined(__AVR_ATmega3290__) || \
|
||||
defined(__AVR_ATmega6490__) || defined(__AVR_ATmega169A__) || defined(__AVR_ATmega169PA__) || \
|
||||
defined(__AVR_ATmega329A__) || defined(__AVR_ATmega329PA__) || defined(__AVR_ATmega3290A__) || \
|
||||
defined(__AVR_ATmega3290PA__) || defined(__AVR_ATmega649A__) || defined(__AVR_ATmega649P__) || \
|
||||
defined(__AVR_ATmega6490A__) || defined(__AVR_ATmega6490P__) || defined(__AVR_ATmega165__) || \
|
||||
defined(__AVR_ATmega325__) || defined(__AVR_ATmega645__) || defined(__AVR_ATmega3250__) || \
|
||||
defined(__AVR_ATmega6450__) || defined(__AVR_ATmega165A__) || defined(__AVR_ATmega165PA__) || \
|
||||
defined(__AVR_ATmega325A__) || defined(__AVR_ATmega325PA__) || defined(__AVR_ATmega3250A__) || \
|
||||
defined(__AVR_ATmega3250PA__) || defined(__AVR_ATmega645A__) || defined(__AVR_ATmega645PA__) || \
|
||||
defined(__AVR_ATmega6450A__) || defined(__AVR_ATmega6450PA__) || defined(__AVR_ATmega644__)
|
||||
/* ATmega with one USART */
|
||||
#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
|
||||
#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
|
||||
#define UART0_STATUS UCSR0A
|
||||
#define UART0_CONTROL UCSR0B
|
||||
#define UART0_CONTROLC UCSR0C
|
||||
#define UART0_DATA UDR0
|
||||
#define UART0_UDRIE UDRIE0
|
||||
#define UART0_UBRRL UBRR0L
|
||||
#define UART0_UBRRH UBRR0H
|
||||
#define UART0_BIT_U2X U2X0
|
||||
#define UART0_BIT_RXCIE RXCIE0
|
||||
#define UART0_BIT_RXEN RXEN0
|
||||
#define UART0_BIT_TXEN TXEN0
|
||||
#define UART0_BIT_UCSZ0 UCSZ00
|
||||
#define UART0_BIT_UCSZ1 UCSZ01
|
||||
#elif defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__) || defined(__AVR_ATmega128A__) || \
|
||||
defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega1281__) || \
|
||||
defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__) || defined(__AVR_ATmega164P__) || \
|
||||
defined(__AVR_ATmega324P__) || defined(__AVR_ATmega644P__) || defined(__AVR_ATmega164A__) || \
|
||||
defined(__AVR_ATmega164PA__) || defined(__AVR_ATmega324A__) || defined(__AVR_ATmega324PA__) || \
|
||||
defined(__AVR_ATmega644A__) || defined(__AVR_ATmega644PA__) || defined(__AVR_ATmega1284__) || \
|
||||
defined(__AVR_ATmega1284P__) || defined(__AVR_ATtiny1634__)
|
||||
/* ATmega with two USART */
|
||||
#define ATMEGA_USART1
|
||||
#define UART0_RECEIVE_INTERRUPT USART0_RX_vect
|
||||
#define UART1_RECEIVE_INTERRUPT USART1_RX_vect
|
||||
#define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect
|
||||
#define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect
|
||||
#define UART0_STATUS UCSR0A
|
||||
#define UART0_CONTROL UCSR0B
|
||||
#define UART0_CONTROLC UCSR0C
|
||||
#define UART0_DATA UDR0
|
||||
#define UART0_UDRIE UDRIE0
|
||||
#define UART0_UBRRL UBRR0L
|
||||
#define UART0_UBRRH UBRR0H
|
||||
#define UART0_BIT_U2X U2X0
|
||||
#define UART0_BIT_RXCIE RXCIE0
|
||||
#define UART0_BIT_RXEN RXEN0
|
||||
#define UART0_BIT_TXEN TXEN0
|
||||
#define UART0_BIT_UCSZ0 UCSZ00
|
||||
#define UART0_BIT_UCSZ1 UCSZ01
|
||||
#define UART1_STATUS UCSR1A
|
||||
#define UART1_CONTROL UCSR1B
|
||||
#define UART1_CONTROLC UCSR1C
|
||||
#define UART1_DATA UDR1
|
||||
#define UART1_UDRIE UDRIE1
|
||||
#define UART1_UBRRL UBRR1L
|
||||
#define UART1_UBRRH UBRR1H
|
||||
#define UART1_BIT_U2X U2X1
|
||||
#define UART1_BIT_RXCIE RXCIE1
|
||||
#define UART1_BIT_RXEN RXEN1
|
||||
#define UART1_BIT_TXEN TXEN1
|
||||
#define UART1_BIT_UCSZ0 UCSZ10
|
||||
#define UART1_BIT_UCSZ1 UCSZ11
|
||||
#elif defined(__AVR_ATmega8U2__) || defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega32U2__) || \
|
||||
defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__) || \
|
||||
defined(__AVR_AT90USB82__) || defined(__AVR_AT90USB162__) || \
|
||||
defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__)
|
||||
#define UART0_RECEIVE_INTERRUPT USART1_RX_vect
|
||||
#define UART0_TRANSMIT_INTERRUPT USART1_UDRE_vect
|
||||
#define UART0_STATUS UCSR1A
|
||||
#define UART0_CONTROL UCSR1B
|
||||
#define UART0_CONTROLC UCSR1C
|
||||
#define UART0_DATA UDR1
|
||||
#define UART0_UDRIE UDRIE1
|
||||
#define UART0_UBRRL UBRR1L
|
||||
#define UART0_UBRRH UBRR1H
|
||||
#define UART0_BIT_U2X U2X1
|
||||
#define UART0_BIT_RXCIE RXCIE1
|
||||
#define UART0_BIT_RXEN RXEN1
|
||||
#define UART0_BIT_TXEN TXEN1
|
||||
#define UART0_BIT_UCSZ0 UCSZ10
|
||||
#define UART0_BIT_UCSZ1 UCSZ11
|
||||
defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__) || defined(__AVR_AT90USB82__) || \
|
||||
defined(__AVR_AT90USB162__) || defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) || \
|
||||
defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__)
|
||||
#define UART0_RECEIVE_INTERRUPT USART1_RX_vect
|
||||
#define UART0_TRANSMIT_INTERRUPT USART1_UDRE_vect
|
||||
#define UART0_STATUS UCSR1A
|
||||
#define UART0_CONTROL UCSR1B
|
||||
#define UART0_CONTROLC UCSR1C
|
||||
#define UART0_DATA UDR1
|
||||
#define UART0_UDRIE UDRIE1
|
||||
#define UART0_UBRRL UBRR1L
|
||||
#define UART0_UBRRH UBRR1H
|
||||
#define UART0_BIT_U2X U2X1
|
||||
#define UART0_BIT_RXCIE RXCIE1
|
||||
#define UART0_BIT_RXEN RXEN1
|
||||
#define UART0_BIT_TXEN TXEN1
|
||||
#define UART0_BIT_UCSZ0 UCSZ10
|
||||
#define UART0_BIT_UCSZ1 UCSZ11
|
||||
#else
|
||||
#error "no UART definition for MCU available"
|
||||
#error "no UART definition for MCU available"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* module global variables
|
||||
*/
|
||||
@ -347,7 +345,7 @@ static volatile unsigned char UART_RxHead;
|
||||
static volatile unsigned char UART_RxTail;
|
||||
static volatile unsigned char UART_LastRxError;
|
||||
|
||||
#if defined( ATMEGA_USART1 )
|
||||
#if defined(ATMEGA_USART1)
|
||||
static volatile unsigned char UART1_TxBuf[UART_TX_BUFFER_SIZE];
|
||||
static volatile unsigned char UART1_RxBuf[UART_RX_BUFFER_SIZE];
|
||||
static volatile unsigned char UART1_TxHead;
|
||||
@ -357,9 +355,7 @@ static volatile unsigned char UART1_RxTail;
|
||||
static volatile unsigned char UART1_LastRxError;
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
ISR (UART0_RECEIVE_INTERRUPT)
|
||||
ISR(UART0_RECEIVE_INTERRUPT)
|
||||
/*************************************************************************
|
||||
Function: UART Receive Complete interrupt
|
||||
Purpose: called when the UART has received a character
|
||||
@ -370,29 +366,28 @@ Purpose: called when the UART has received a character
|
||||
unsigned char usr;
|
||||
unsigned char lastRxError;
|
||||
|
||||
|
||||
/* read UART status register and UART data register */
|
||||
usr = UART0_STATUS;
|
||||
data = UART0_DATA;
|
||||
|
||||
/* get FEn (Frame Error) DORn (Data OverRun) UPEn (USART Parity Error) bits */
|
||||
#if defined(FE) && defined(DOR) && defined(UPE)
|
||||
lastRxError = usr & (_BV(FE)|_BV(DOR)|_BV(UPE) );
|
||||
lastRxError = usr & (_BV(FE) | _BV(DOR) | _BV(UPE));
|
||||
#elif defined(FE0) && defined(DOR0) && defined(UPE0)
|
||||
lastRxError = usr & (_BV(FE0)|_BV(DOR0)|_BV(UPE0) );
|
||||
lastRxError = usr & (_BV(FE0) | _BV(DOR0) | _BV(UPE0));
|
||||
#elif defined(FE1) && defined(DOR1) && defined(UPE1)
|
||||
lastRxError = usr & (_BV(FE1)|_BV(DOR1)|_BV(UPE1) );
|
||||
lastRxError = usr & (_BV(FE1) | _BV(DOR1) | _BV(UPE1));
|
||||
#elif defined(FE) && defined(DOR)
|
||||
lastRxError = usr & (_BV(FE)|_BV(DOR) );
|
||||
lastRxError = usr & (_BV(FE) | _BV(DOR));
|
||||
#endif
|
||||
|
||||
/* calculate buffer index */
|
||||
tmphead = ( UART_RxHead + 1) & UART_RX_BUFFER_MASK;
|
||||
tmphead = (UART_RxHead + 1) & UART_RX_BUFFER_MASK;
|
||||
|
||||
if ( tmphead == UART_RxTail ) {
|
||||
if (tmphead == UART_RxTail) {
|
||||
/* error: receive buffer overflow */
|
||||
lastRxError = UART_BUFFER_OVERFLOW >> 8;
|
||||
}else{
|
||||
} else {
|
||||
/* store new index */
|
||||
UART_RxHead = tmphead;
|
||||
/* store received data in buffer */
|
||||
@ -401,8 +396,7 @@ Purpose: called when the UART has received a character
|
||||
UART_LastRxError |= lastRxError;
|
||||
}
|
||||
|
||||
|
||||
ISR (UART0_TRANSMIT_INTERRUPT)
|
||||
ISR(UART0_TRANSMIT_INTERRUPT)
|
||||
/*************************************************************************
|
||||
Function: UART Data Register Empty interrupt
|
||||
Purpose: called when the UART is ready to transmit the next byte
|
||||
@ -410,20 +404,18 @@ Purpose: called when the UART is ready to transmit the next byte
|
||||
{
|
||||
unsigned char tmptail;
|
||||
|
||||
|
||||
if ( UART_TxHead != UART_TxTail) {
|
||||
if (UART_TxHead != UART_TxTail) {
|
||||
/* calculate and store new buffer index */
|
||||
tmptail = (UART_TxTail + 1) & UART_TX_BUFFER_MASK;
|
||||
UART_TxTail = tmptail;
|
||||
/* get one byte from buffer and write it to UART */
|
||||
UART0_DATA = UART_TxBuf[tmptail]; /* start transmission */
|
||||
}else{
|
||||
} else {
|
||||
/* tx buffer empty, disable UDRE interrupt */
|
||||
UART0_CONTROL &= ~_BV(UART0_UDRIE);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart_init()
|
||||
Purpose: initialize UART and set baudrate
|
||||
@ -455,31 +447,29 @@ void uart_init(unsigned int baudrate)
|
||||
#endif
|
||||
|
||||
/* Set baud rate */
|
||||
if ( baudrate & 0x8000 )
|
||||
{
|
||||
#if UART0_BIT_U2X
|
||||
UART0_STATUS = (1<<UART0_BIT_U2X); //Enable 2x speed
|
||||
#endif
|
||||
if (baudrate & 0x8000) {
|
||||
#if UART0_BIT_U2X
|
||||
UART0_STATUS = (1 << UART0_BIT_U2X); // Enable 2x speed
|
||||
#endif
|
||||
}
|
||||
#if defined(UART0_UBRRH)
|
||||
UART0_UBRRH = (unsigned char)((baudrate>>8)&0x80) ;
|
||||
#endif
|
||||
UART0_UBRRL = (unsigned char) (baudrate&0x00FF);
|
||||
#if defined(UART0_UBRRH)
|
||||
UART0_UBRRH = (unsigned char)((baudrate >> 8) & 0x80);
|
||||
#endif
|
||||
UART0_UBRRL = (unsigned char)(baudrate & 0x00FF);
|
||||
|
||||
/* Enable USART receiver and transmitter and receive complete interrupt */
|
||||
UART0_CONTROL = _BV(UART0_BIT_RXCIE)|(1<<UART0_BIT_RXEN)|(1<<UART0_BIT_TXEN);
|
||||
UART0_CONTROL = _BV(UART0_BIT_RXCIE) | (1 << UART0_BIT_RXEN) | (1 << UART0_BIT_TXEN);
|
||||
|
||||
/* Set frame format: asynchronous, 8data, no parity, 1stop bit */
|
||||
#ifdef UART0_CONTROLC
|
||||
#ifdef UART0_BIT_URSEL
|
||||
UART0_CONTROLC = (1<<UART0_BIT_URSEL)|(1<<UART0_BIT_UCSZ1)|(1<<UART0_BIT_UCSZ0);
|
||||
#else
|
||||
UART0_CONTROLC = (1<<UART0_BIT_UCSZ1)|(1<<UART0_BIT_UCSZ0);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
}/* uart_init */
|
||||
/* Set frame format: asynchronous, 8data, no parity, 1stop bit */
|
||||
#ifdef UART0_CONTROLC
|
||||
#ifdef UART0_BIT_URSEL
|
||||
UART0_CONTROLC = (1 << UART0_BIT_URSEL) | (1 << UART0_BIT_UCSZ1) | (1 << UART0_BIT_UCSZ0);
|
||||
#else
|
||||
UART0_CONTROLC = (1 << UART0_BIT_UCSZ1) | (1 << UART0_BIT_UCSZ0);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
} /* uart_init */
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart_getc()
|
||||
@ -493,8 +483,7 @@ unsigned int uart_getc(void)
|
||||
unsigned char data;
|
||||
unsigned char lastRxError;
|
||||
|
||||
|
||||
if ( UART_RxHead == UART_RxTail ) {
|
||||
if (UART_RxHead == UART_RxTail) {
|
||||
return UART_NO_DATA; /* no data available */
|
||||
}
|
||||
|
||||
@ -511,8 +500,7 @@ unsigned int uart_getc(void)
|
||||
UART_LastRxError = 0;
|
||||
return (lastRxError << 8) + data;
|
||||
|
||||
}/* uart_getc */
|
||||
|
||||
} /* uart_getc */
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart_putc()
|
||||
@ -524,11 +512,10 @@ void uart_putc(unsigned char data)
|
||||
{
|
||||
unsigned char tmphead;
|
||||
|
||||
|
||||
tmphead = (UART_TxHead + 1) & UART_TX_BUFFER_MASK;
|
||||
|
||||
while ( tmphead == UART_TxTail ){
|
||||
;/* wait for free space in buffer */
|
||||
while (tmphead == UART_TxTail) {
|
||||
; /* wait for free space in buffer */
|
||||
}
|
||||
|
||||
UART_TxBuf[tmphead] = data;
|
||||
@ -537,8 +524,7 @@ void uart_putc(unsigned char data)
|
||||
/* enable UDRE interrupt */
|
||||
UART0_CONTROL |= _BV(UART0_UDRIE);
|
||||
|
||||
}/* uart_putc */
|
||||
|
||||
} /* uart_putc */
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart_puts()
|
||||
@ -546,13 +532,12 @@ Purpose: transmit string to UART
|
||||
Input: string to be transmitted
|
||||
Returns: none
|
||||
**************************************************************************/
|
||||
void uart_puts(const char *s )
|
||||
void uart_puts(const char *s)
|
||||
{
|
||||
while (*s)
|
||||
uart_putc(*s++);
|
||||
|
||||
}/* uart_puts */
|
||||
|
||||
} /* uart_puts */
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart_puts_p()
|
||||
@ -560,20 +545,19 @@ Purpose: transmit string from program memory to UART
|
||||
Input: program memory string to be transmitted
|
||||
Returns: none
|
||||
**************************************************************************/
|
||||
void uart_puts_p(const char *progmem_s )
|
||||
void uart_puts_p(const char *progmem_s)
|
||||
{
|
||||
register char c;
|
||||
|
||||
while ( (c = pgm_read_byte(progmem_s++)) )
|
||||
while ((c = pgm_read_byte(progmem_s++)))
|
||||
uart_putc(c);
|
||||
|
||||
}/* uart_puts_p */
|
||||
|
||||
} /* uart_puts_p */
|
||||
|
||||
/*
|
||||
* these functions are only for ATmegas with two USART
|
||||
*/
|
||||
#if defined( ATMEGA_USART1 )
|
||||
#if defined(ATMEGA_USART1)
|
||||
|
||||
ISR(UART1_RECEIVE_INTERRUPT)
|
||||
/*************************************************************************
|
||||
@ -586,21 +570,20 @@ Purpose: called when the UART1 has received a character
|
||||
unsigned char usr;
|
||||
unsigned char lastRxError;
|
||||
|
||||
|
||||
/* read UART status register and UART data register */
|
||||
usr = UART1_STATUS;
|
||||
data = UART1_DATA;
|
||||
|
||||
/* get FEn (Frame Error) DORn (Data OverRun) UPEn (USART Parity Error) bits */
|
||||
lastRxError = usr & (_BV(FE1)|_BV(DOR1)|_BV(UPE1) );
|
||||
lastRxError = usr & (_BV(FE1) | _BV(DOR1) | _BV(UPE1));
|
||||
|
||||
/* calculate buffer index */
|
||||
tmphead = ( UART1_RxHead + 1) & UART_RX_BUFFER_MASK;
|
||||
tmphead = (UART1_RxHead + 1) & UART_RX_BUFFER_MASK;
|
||||
|
||||
if ( tmphead == UART1_RxTail ) {
|
||||
if (tmphead == UART1_RxTail) {
|
||||
/* error: receive buffer overflow */
|
||||
lastRxError = UART_BUFFER_OVERFLOW >> 8;
|
||||
}else{
|
||||
} else {
|
||||
/* store new index */
|
||||
UART1_RxHead = tmphead;
|
||||
/* store received data in buffer */
|
||||
@ -609,7 +592,6 @@ Purpose: called when the UART1 has received a character
|
||||
UART1_LastRxError |= lastRxError;
|
||||
}
|
||||
|
||||
|
||||
ISR(UART1_TRANSMIT_INTERRUPT)
|
||||
/*************************************************************************
|
||||
Function: UART1 Data Register Empty interrupt
|
||||
@ -618,20 +600,18 @@ Purpose: called when the UART1 is ready to transmit the next byte
|
||||
{
|
||||
unsigned char tmptail;
|
||||
|
||||
|
||||
if ( UART1_TxHead != UART1_TxTail) {
|
||||
if (UART1_TxHead != UART1_TxTail) {
|
||||
/* calculate and store new buffer index */
|
||||
tmptail = (UART1_TxTail + 1) & UART_TX_BUFFER_MASK;
|
||||
UART1_TxTail = tmptail;
|
||||
/* get one byte from buffer and write it to UART */
|
||||
UART1_DATA = UART1_TxBuf[tmptail]; /* start transmission */
|
||||
}else{
|
||||
} else {
|
||||
/* tx buffer empty, disable UDRE interrupt */
|
||||
UART1_CONTROL &= ~_BV(UART1_UDRIE);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart1_init()
|
||||
Purpose: initialize UART1 and set baudrate
|
||||
@ -663,27 +643,25 @@ void uart1_init(unsigned int baudrate)
|
||||
#endif
|
||||
|
||||
/* Set baud rate */
|
||||
if ( baudrate & 0x8000 )
|
||||
{
|
||||
#if UART1_BIT_U2X
|
||||
UART1_STATUS = (1<<UART1_BIT_U2X); //Enable 2x speed
|
||||
#endif
|
||||
if (baudrate & 0x8000) {
|
||||
#if UART1_BIT_U2X
|
||||
UART1_STATUS = (1 << UART1_BIT_U2X); // Enable 2x speed
|
||||
#endif
|
||||
}
|
||||
UART1_UBRRH = (unsigned char)((baudrate>>8)&0x80) ;
|
||||
UART1_UBRRL = (unsigned char) baudrate;
|
||||
UART1_UBRRH = (unsigned char)((baudrate >> 8) & 0x80);
|
||||
UART1_UBRRL = (unsigned char)baudrate;
|
||||
|
||||
/* Enable USART receiver and transmitter and receive complete interrupt */
|
||||
UART1_CONTROL = _BV(UART1_BIT_RXCIE)|(1<<UART1_BIT_RXEN)|(1<<UART1_BIT_TXEN);
|
||||
UART1_CONTROL = _BV(UART1_BIT_RXCIE) | (1 << UART1_BIT_RXEN) | (1 << UART1_BIT_TXEN);
|
||||
|
||||
/* Set frame format: asynchronous, 8data, no parity, 1stop bit */
|
||||
#ifdef UART1_BIT_URSEL
|
||||
UART1_CONTROLC = (1<<UART1_BIT_URSEL)|(1<<UART1_BIT_UCSZ1)|(1<<UART1_BIT_UCSZ0);
|
||||
#else
|
||||
UART1_CONTROLC = (1<<UART1_BIT_UCSZ1)|(1<<UART1_BIT_UCSZ0);
|
||||
#endif
|
||||
|
||||
}/* uart_init */
|
||||
/* Set frame format: asynchronous, 8data, no parity, 1stop bit */
|
||||
#ifdef UART1_BIT_URSEL
|
||||
UART1_CONTROLC = (1 << UART1_BIT_URSEL) | (1 << UART1_BIT_UCSZ1) | (1 << UART1_BIT_UCSZ0);
|
||||
#else
|
||||
UART1_CONTROLC = (1 << UART1_BIT_UCSZ1) | (1 << UART1_BIT_UCSZ0);
|
||||
#endif
|
||||
|
||||
} /* uart_init */
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart1_getc()
|
||||
@ -697,8 +675,7 @@ unsigned int uart1_getc(void)
|
||||
unsigned int data;
|
||||
unsigned char lastRxError;
|
||||
|
||||
|
||||
if ( UART1_RxHead == UART1_RxTail ) {
|
||||
if (UART1_RxHead == UART1_RxTail) {
|
||||
return UART_NO_DATA; /* no data available */
|
||||
}
|
||||
|
||||
@ -715,8 +692,7 @@ unsigned int uart1_getc(void)
|
||||
UART1_LastRxError = 0;
|
||||
return (lastRxError << 8) + data;
|
||||
|
||||
}/* uart1_getc */
|
||||
|
||||
} /* uart1_getc */
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart1_putc()
|
||||
@ -728,11 +704,10 @@ void uart1_putc(unsigned char data)
|
||||
{
|
||||
unsigned char tmphead;
|
||||
|
||||
|
||||
tmphead = (UART1_TxHead + 1) & UART_TX_BUFFER_MASK;
|
||||
|
||||
while ( tmphead == UART1_TxTail ){
|
||||
;/* wait for free space in buffer */
|
||||
while (tmphead == UART1_TxTail) {
|
||||
; /* wait for free space in buffer */
|
||||
}
|
||||
|
||||
UART1_TxBuf[tmphead] = data;
|
||||
@ -741,8 +716,7 @@ void uart1_putc(unsigned char data)
|
||||
/* enable UDRE interrupt */
|
||||
UART1_CONTROL |= _BV(UART1_UDRIE);
|
||||
|
||||
}/* uart1_putc */
|
||||
|
||||
} /* uart1_putc */
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart1_puts()
|
||||
@ -750,13 +724,12 @@ Purpose: transmit string to UART1
|
||||
Input: string to be transmitted
|
||||
Returns: none
|
||||
**************************************************************************/
|
||||
void uart1_puts(const char *s )
|
||||
void uart1_puts(const char *s)
|
||||
{
|
||||
while (*s)
|
||||
uart1_putc(*s++);
|
||||
|
||||
}/* uart1_puts */
|
||||
|
||||
} /* uart1_puts */
|
||||
|
||||
/*************************************************************************
|
||||
Function: uart1_puts_p()
|
||||
@ -764,14 +737,13 @@ Purpose: transmit string from program memory to UART1
|
||||
Input: program memory string to be transmitted
|
||||
Returns: none
|
||||
**************************************************************************/
|
||||
void uart1_puts_p(const char *progmem_s )
|
||||
void uart1_puts_p(const char *progmem_s)
|
||||
{
|
||||
register char c;
|
||||
|
||||
while ( (c = pgm_read_byte(progmem_s++)) )
|
||||
while ((c = pgm_read_byte(progmem_s++)))
|
||||
uart1_putc(c);
|
||||
|
||||
}/* uart1_puts_p */
|
||||
|
||||
} /* uart1_puts_p */
|
||||
|
||||
#endif
|
||||
|
||||
31
uart.h
31
uart.h
@ -46,33 +46,30 @@ LICENSE:
|
||||
* @copyright (C) 2015 Peter Fleury, GNU General Public License Version 3
|
||||
*/
|
||||
|
||||
|
||||
#include <avr/pgmspace.h>
|
||||
|
||||
#if (__GNUC__ * 100 + __GNUC_MINOR__) < 405
|
||||
#error "This library requires AVR-GCC 4.5 or later, update to newer AVR-GCC compiler !"
|
||||
#endif
|
||||
|
||||
|
||||
/**@{*/
|
||||
|
||||
|
||||
/*
|
||||
** constants and macros
|
||||
*/
|
||||
|
||||
|
||||
/** @brief UART Baudrate Expression
|
||||
* @param xtalCpu system clock in Mhz, e.g. 4000000UL for 4Mhz
|
||||
* @param baudRate baudrate in bps, e.g. 1200, 2400, 9600
|
||||
*/
|
||||
#define UART_BAUD_SELECT(baudRate,xtalCpu) (((xtalCpu) + 8UL * (baudRate)) / (16UL * (baudRate)) -1UL)
|
||||
#define UART_BAUD_SELECT(baudRate, xtalCpu) (((xtalCpu) + 8UL * (baudRate)) / (16UL * (baudRate)) - 1UL)
|
||||
|
||||
/** @brief UART Baudrate Expression for ATmega double speed mode
|
||||
* @param xtalCpu system clock in Mhz, e.g. 4000000UL for 4Mhz
|
||||
* @param baudRate baudrate in bps, e.g. 1200, 2400, 9600
|
||||
*/
|
||||
#define UART_BAUD_SELECT_DOUBLE_SPEED(baudRate,xtalCpu) ( ((((xtalCpu) + 4UL * (baudRate)) / (8UL * (baudRate)) -1UL)) | 0x8000)
|
||||
#define UART_BAUD_SELECT_DOUBLE_SPEED(baudRate, xtalCpu) \
|
||||
(((((xtalCpu) + 4UL * (baudRate)) / (8UL * (baudRate)) - 1UL)) | 0x8000)
|
||||
|
||||
/** @brief Size of the circular receive buffer, must be power of 2
|
||||
*
|
||||
@ -93,7 +90,7 @@ LICENSE:
|
||||
#endif
|
||||
|
||||
/* test if the size of the circular buffers fits into SRAM */
|
||||
#if ( (UART_RX_BUFFER_SIZE+UART_TX_BUFFER_SIZE) >= (RAMEND-0x60 ) )
|
||||
#if ((UART_RX_BUFFER_SIZE + UART_TX_BUFFER_SIZE) >= (RAMEND - 0x60))
|
||||
#error "size of UART_RX_BUFFER_SIZE + UART_TX_BUFFER_SIZE larger than size of SRAM"
|
||||
#endif
|
||||
|
||||
@ -106,7 +103,6 @@ LICENSE:
|
||||
#define UART_BUFFER_OVERFLOW 0x0200 /**< @brief receive ringbuffer overflow */
|
||||
#define UART_NO_DATA 0x0100 /**< @brief no receive data available */
|
||||
|
||||
|
||||
/*
|
||||
** function prototypes
|
||||
*/
|
||||
@ -118,7 +114,6 @@ LICENSE:
|
||||
*/
|
||||
extern void uart_init(unsigned int baudrate);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get received byte from ringbuffer
|
||||
*
|
||||
@ -145,7 +140,6 @@ extern void uart_init(unsigned int baudrate);
|
||||
*/
|
||||
extern unsigned int uart_getc(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Put byte to ringbuffer for transmitting via UART
|
||||
* @param data byte to be transmitted
|
||||
@ -153,7 +147,6 @@ extern unsigned int uart_getc(void);
|
||||
*/
|
||||
extern void uart_putc(unsigned char data);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Put string to ringbuffer for transmitting via UART
|
||||
*
|
||||
@ -164,8 +157,7 @@ extern void uart_putc(unsigned char data);
|
||||
* @param s string to be transmitted
|
||||
* @return none
|
||||
*/
|
||||
extern void uart_puts(const char *s );
|
||||
|
||||
extern void uart_puts(const char *s);
|
||||
|
||||
/**
|
||||
* @brief Put string from program memory to ringbuffer for transmitting via UART.
|
||||
@ -178,15 +170,13 @@ extern void uart_puts(const char *s );
|
||||
* @return none
|
||||
* @see uart_puts_P
|
||||
*/
|
||||
extern void uart_puts_p(const char *s );
|
||||
extern void uart_puts_p(const char *s);
|
||||
|
||||
/**
|
||||
* @brief Macro to automatically put a string constant into program memory
|
||||
*/
|
||||
#define uart_puts_P(__s) uart_puts_p(PSTR(__s))
|
||||
|
||||
|
||||
|
||||
/** @brief Initialize USART1 (only available on selected ATmegas) @see uart_init */
|
||||
extern void uart1_init(unsigned int baudrate);
|
||||
/** @brief Get received byte of USART1 from ringbuffer. (only available on selected ATmega) @see uart_getc */
|
||||
@ -194,14 +184,13 @@ extern unsigned int uart1_getc(void);
|
||||
/** @brief Put byte to ringbuffer for transmitting via USART1 (only available on selected ATmega) @see uart_putc */
|
||||
extern void uart1_putc(unsigned char data);
|
||||
/** @brief Put string to ringbuffer for transmitting via USART1 (only available on selected ATmega) @see uart_puts */
|
||||
extern void uart1_puts(const char *s );
|
||||
/** @brief Put string from program memory to ringbuffer for transmitting via USART1 (only available on selected ATmega) @see uart_puts_p */
|
||||
extern void uart1_puts_p(const char *s );
|
||||
extern void uart1_puts(const char *s);
|
||||
/** @brief Put string from program memory to ringbuffer for transmitting via USART1 (only available on selected ATmega)
|
||||
* @see uart_puts_p */
|
||||
extern void uart1_puts_p(const char *s);
|
||||
/** @brief Macro to automatically put a string constant into program memory */
|
||||
#define uart1_puts_P(__s) uart1_puts_p(PSTR(__s))
|
||||
|
||||
/**@}*/
|
||||
|
||||
|
||||
#endif // UART_H
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user