avr/uart
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fixed flushing not blocking correctly

Browse Source
This commit is contained in:
BlackMark 2019-08-03 18:45:51 +02:00
parent 9f9f7a8de5
commit 8153696309
3 changed files with 29 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
hardware.hpp
View File

@ -64,14 +64,24 @@ class Hardware {
return *Registers::IO_REG; return *Registers::IO_REG;
} }
static bool txActive() FORCE_INLINE static bool txEmpty() FORCE_INLINE
{ {
return !(*Registers::CTRL_STAT_REG_A & (1 << CtrlFlagsA::DATA_REG_EMPTY)); return *Registers::CTRL_STAT_REG_A & (1 << CtrlFlagsA::DATA_REG_EMPTY);
}
static bool txComplete() FORCE_INLINE
{
return *Registers::CTRL_STAT_REG_A & (1 << CtrlFlagsA::TRANSMIT_COMPLETE);
}
static void clearTxComplete() FORCE_INLINE
{
*Registers::CTRL_STAT_REG_A |= (1 << CtrlFlagsA::TRANSMIT_COMPLETE);
} }
static void txByteBlocking(const typename cfg::data_t &byte) FORCE_INLINE static void txByteBlocking(const typename cfg::data_t &byte) FORCE_INLINE
{ {
while (txActive()) while (!txEmpty())
; ;
*Registers::IO_REG = byte; *Registers::IO_REG = byte;

10
hardware0.hpp
View File

@ -107,8 +107,11 @@ class Hardware0 {
static void flushTx() FORCE_INLINE static void flushTx() FORCE_INLINE
{ {
while (HardwareImpl::txActive()) while (!HardwareImpl::txEmpty())
; ;
while (!HardwareImpl::txComplete())
;
HardwareImpl::clearTxComplete();
} }
private: private:
@ -174,8 +177,11 @@ class Hardware0<mode, cfg, Driven::INTERRUPT> {
{ {
while (sm_txBuf.head != sm_txBuf.tail) while (sm_txBuf.head != sm_txBuf.tail)
; ;
while (HardwareImpl::txActive()) while (!HardwareImpl::txEmpty())
; ;
while (!HardwareImpl::txComplete())
;
HardwareImpl::clearTxComplete();
} }
private: private:

10
hardware1.hpp
View File

@ -111,8 +111,11 @@ class Hardware1 {
static void flushTx() FORCE_INLINE static void flushTx() FORCE_INLINE
{ {
while (HardwareImpl::txActive()) while (!HardwareImpl::txEmpty())
; ;
while (!HardwareImpl::txComplete())
;
HardwareImpl::clearTxComplete();
} }
private: private:
@ -178,8 +181,11 @@ class Hardware1<mode, cfg, Driven::INTERRUPT> {
{ {
while (sm_txBuf.head != sm_txBuf.tail) while (sm_txBuf.head != sm_txBuf.tail)
; ;
while (HardwareImpl::txActive()) while (!HardwareImpl::txEmpty())
; ;
while (!HardwareImpl::txComplete())
;
HardwareImpl::clearTxComplete();
} }
private: private: