2019-07-27 18:55:17 +02:00
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#pragma once
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2019-07-28 12:15:19 +02:00
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#include "config.hpp"
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2019-07-27 18:55:17 +02:00
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2019-07-28 17:32:51 +02:00
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#define FORCE_INLINE __attribute__((always_inline))
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2019-07-27 18:55:17 +02:00
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namespace uart {
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2019-07-28 12:15:19 +02:00
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enum class Mode {
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ASYNCHRONOUS,
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ASYNCHRONOUS_2X,
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SYNCHRONOUS_MASTER,
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SYNCHRONOUS_SLAVE,
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SPI,
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};
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2019-07-28 14:09:09 +02:00
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enum class Driven {
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INTERRUPT,
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BLOCKING,
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};
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2019-07-28 17:32:51 +02:00
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namespace detail {
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2019-07-30 20:29:38 +02:00
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#if defined(__AVR_ATmega1284P__)
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struct Registers0 {
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static constexpr volatile auto *IO_REG = &UDR0;
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static constexpr volatile auto *CTRL_STAT_REG_A = &UCSR0A;
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static constexpr volatile auto *CTRL_STAT_REG_B = &UCSR0B;
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static constexpr volatile auto *CTRL_STAT_REG_C = &UCSR0C;
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static constexpr volatile auto *BAUD_REG_L = &UBRR0L;
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static constexpr volatile auto *BAUD_REG_H = &UBRR0H;
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};
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2019-07-30 21:43:52 +02:00
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enum class ControlFlagsA0 {
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MULTI_PROC_COMM_MODE = MPCM0,
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SPEED_2X = U2X0,
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PARITY_ERROR = UPE0,
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DATA_OVER_RUN = DOR0,
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FRAME_ERROR = FE0,
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DATA_REG_EMPTY = UDRE0,
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TRANSMIT_COMPLETE = TXC0,
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RECEIVE_COMPLETE = RXC0,
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};
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enum class ControlFlagsB0 {
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TX_DATA_BIT_8 = TXB80,
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RX_DATA_BIT_8 = RXB80,
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CHAR_SIZE_2 = UCSZ02,
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TX_ENABLE = TXEN0,
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RX_ENABLE = RXEN0,
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DATA_REG_EMPTY_INT_ENABLE = UDRIE0,
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TX_INT_ENABLE = TXCIE0,
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RX_INT_ENABLE = RXCIE0,
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};
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enum class ControlFlagsC0 {
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CLK_POLARITY = UCPOL0,
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CHAR_SIZE_0 = UCSZ00,
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CHAR_SIZE_1 = UCSZ01,
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STOP_BIT_SEL = USBS0,
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PARITY_MODE_0 = UPM00,
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PARITY_MODE_1 = UPM01,
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MODE_SEL_0 = UMSEL00,
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MODE_SEL_1 = UMSEL01,
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};
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constexpr int operator<<(const int &lhs, const ControlFlagsA0 &rhs)
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{
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return lhs << static_cast<int>(rhs);
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}
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constexpr int operator<<(const int &lhs, const ControlFlagsB0 &rhs)
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{
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return lhs << static_cast<int>(rhs);
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}
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constexpr int operator<<(const int &lhs, const ControlFlagsC0 &rhs)
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{
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return lhs << static_cast<int>(rhs);
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}
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#else
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#error "This chip is not supported"
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#endif
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2019-07-30 21:43:52 +02:00
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template <class Registers, typename CtrlFlagsA, typename CtrlFlagsB, typename CtrlFlagsC, class cfg, Mode mode>
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class Hardware {
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public:
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static void init()
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{
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constexpr auto baudVal = calcBaud();
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*Registers::BAUD_REG_H = static_cast<uint8_t>(baudVal >> 8);
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*Registers::BAUD_REG_L = static_cast<uint8_t>(baudVal);
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constexpr auto dataBitsVal = calcDataBits();
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constexpr auto parityVal = calcParity();
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constexpr auto stopBitsVal = calcStopBits();
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constexpr auto modeVal = calcMode();
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constexpr auto enableRx = calcRxState<true>();
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constexpr auto enableTx = calcTxState<true>();
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constexpr uint8_t controlRegB = dataBitsVal.regBVal | enableRx | enableTx;
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constexpr uint8_t controlRegC = dataBitsVal.regCVal | parityVal | stopBitsVal | modeVal;
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2019-07-30 21:43:52 +02:00
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*Registers::CTRL_STAT_REG_B = controlRegB;
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*Registers::CTRL_STAT_REG_C = controlRegC;
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}
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static void txByte(typename cfg::data_t byte)
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{
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while (!(*Registers::CTRL_STAT_REG_A & (1 << CtrlFlagsA::DATA_REG_EMPTY)))
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;
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*Registers::IO_REG = byte;
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}
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private:
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struct DataBitsVal {
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uint8_t regCVal = 0;
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uint8_t regBVal = 0;
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};
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static constexpr auto calcBaud()
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{
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// The actual formula is (F_CPU / (16 * baudRate)) - 1, but this one has the advantage of rounding correctly
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constexpr auto baudVal = (F_CPU + 8 * cfg::BAUD_RATE) / (16 * cfg::BAUD_RATE) - 1;
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return baudVal;
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}
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static constexpr auto calcDataBits()
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{
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DataBitsVal dataBitsVal;
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switch (cfg::DATA_BITS) {
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case DataBits::FIVE:
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dataBitsVal.regCVal = 0;
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break;
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case DataBits::SIX:
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dataBitsVal.regCVal = (1 << CtrlFlagsC::CHAR_SIZE_0);
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break;
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case DataBits::SEVEN:
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dataBitsVal.regCVal = (1 << CtrlFlagsC::CHAR_SIZE_1);
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break;
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case DataBits::EIGHT:
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dataBitsVal.regCVal = (1 << CtrlFlagsC::CHAR_SIZE_1) | (1 << CtrlFlagsC::CHAR_SIZE_0);
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break;
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case DataBits::NINE:
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dataBitsVal.regCVal = (1 << CtrlFlagsC::CHAR_SIZE_1) | (1 << CtrlFlagsC::CHAR_SIZE_0);
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dataBitsVal.regBVal = (1 << CtrlFlagsB::CHAR_SIZE_2);
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break;
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}
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return dataBitsVal;
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}
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static constexpr auto calcParity()
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{
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uint8_t parityVal = 0;
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2019-07-30 21:43:52 +02:00
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if (cfg::PARITY == Parity::EVEN)
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parityVal = (1 << CtrlFlagsC::PARITY_MODE_1);
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else if (cfg::PARITY == Parity::ODD)
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parityVal = (1 << CtrlFlagsC::PARITY_MODE_1) | (1 << CtrlFlagsC::PARITY_MODE_0);
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return parityVal;
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}
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static constexpr auto calcStopBits()
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{
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uint8_t stopBitsVal = 0;
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2019-07-30 21:43:52 +02:00
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if (cfg::STOP_BITS == StopBits::TWO)
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stopBitsVal = (1 << CtrlFlagsC::STOP_BIT_SEL);
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return stopBitsVal;
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}
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static constexpr auto calcMode()
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{
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static_assert(mode != Mode::SPI, "SPI mode can not be used with uart");
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uint8_t modeVal = 0;
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if (mode == Mode::SYNCHRONOUS_MASTER || mode == Mode::SYNCHRONOUS_SLAVE) {
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modeVal = (1 << CtrlFlagsC::MODE_SEL_0);
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}
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return modeVal;
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}
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template <bool enable>
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static constexpr auto calcRxState()
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{
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uint8_t enableVal = 0;
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if (enable)
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enableVal = (1 << CtrlFlagsB::RX_ENABLE);
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return enableVal;
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}
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template <bool enable>
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static constexpr auto calcTxState()
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{
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uint8_t enableVal = 0;
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if (enable)
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enableVal = (1 << CtrlFlagsB::TX_ENABLE);
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return enableVal;
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}
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2019-07-27 18:55:17 +02:00
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};
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2019-07-30 21:43:52 +02:00
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} // namespace detail
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template <Mode mode = Mode::ASYNCHRONOUS, class cfg = Config<>, Driven driven = Driven::INTERRUPT>
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class Hardware0 {
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public:
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using data_t = typename cfg::data_t;
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static constexpr auto DATA_BITS = cfg::DATA_BITS;
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static void init()
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{
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HardwareImpl::init();
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}
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static void txByte(data_t byte) FORCE_INLINE
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{
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HardwareImpl::txByte(byte);
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}
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static data_t rxByte() {}
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static data_t peek() {}
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private:
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using HardwareImpl = detail::Hardware<detail::Registers0, detail::ControlFlagsA0, detail::ControlFlagsB0,
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detail::ControlFlagsC0, cfg, mode>;
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};
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2019-07-27 18:55:17 +02:00
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} // namespace uart
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2019-07-28 17:32:51 +02:00
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#undef FORCE_INLINE
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