2017-04-27 00:05:38 +02:00
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/*
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* DS RTC Library: DS1307 and DS3231 driver library
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* (C) 2011 Akafugu Corporation
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*
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* This program is free software; you can redistribute it and/or modify it under the
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* terms of the GNU General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any later
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* version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT ANY
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* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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* PARTICULAR PURPOSE. See the GNU General Public License for more details.
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*
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*/
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/*
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* DS1307 register map
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2020-05-15 11:50:11 +02:00
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*
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2017-04-27 00:05:38 +02:00
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* 00h-06h: seconds, minutes, hours, day-of-week, date, month, year (all in BCD)
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* bit 7 of seconds enables/disables clock
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* bit 6 of hours toggles 12/24h mode (1 for 12h, 0 for 24h)
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* when 12h mode is selected bit 5 is high for PM, low for AM
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* 07h: control
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* bit7: OUT
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* bit6: 0
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* bit5: 0
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* bit4: SQWE
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* bit3: 0
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* bit2: 0
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* bit1: RS0
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* bit0: RS1
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* 08h-3fh: 56 bytes of SRAM
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*
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* DS3231 register map
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*
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* 00h-06h: seconds, minutes, hours, day-of-week, date, month, year (all in BCD)
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* bit 7 should be set to zero: The DS3231 clock is always running
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* 07h: A1M1 Alarm 1 seconds
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* 08h: A1M2 Alarm 1 minutes
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* 09h: A1M3 Alarm 1 hour (bit6 is am/pm flag in 12h mode)
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* 0ah: A1M4 Alarm 1 day/date (bit6: 1 for day, 0 for date)
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* 0bh: A2M2 Alarm 2 minutes
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* 0ch: A2M3 Alarm 2 hour (bit6 is am/pm flag in 12h mode)
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* 0dh: A2M4 Alarm 2 day/data (bit6: 1 for day, 0 for date)
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* <see data sheet page12 for Alarm register mask bit tables:
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* for alarm when hours, minutes and seconds match set 1000 for alarm 1>
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* 0eh: control
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* bit7: !EOSC
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* bit6: BBSQW
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* bit5: CONV
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* bit4: RS2
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* bit3: RS1
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* bit2: INTCN
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* bit1: A2IE
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* bit0: A1IE
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* 0fh: control/status
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* bit7: OSF
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* bit6: 0
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* bit5: 0
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* bit4: 0
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* bit3: EN32kHz
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* bit2: BSY
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* bit1: A2F alarm 2 flag
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* bit0: A1F alarm 1 flag
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* 10h: aging offset (signed)
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* 11h: MSB of temp (signed)
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* 12h: LSB of temp in bits 7 and 6 (0.25 degrees for each 00, 01, 10, 11)
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*
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*/
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#include <avr/io.h>
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#define TRUE 1
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#define FALSE 0
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2020-05-15 11:50:11 +02:00
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#include "../clock.hpp"
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#include "../i2c/i2c.hpp"
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using i2c_t = i2c::I2c<i2c::Hardware<100'000>>;
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2017-04-27 00:05:38 +02:00
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#include "rtc.h"
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#define RTC_ADDR 0x68 // I2C address
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#define CH_BIT 7 // clock halt bit
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// statically allocated structure for time value
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2017-12-16 19:48:54 +01:00
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struct rtc_tm _rtc_tm;
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2017-04-27 00:05:38 +02:00
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uint8_t dec2bcd(uint8_t d)
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{
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return ((d/10 * 16) + (d % 10));
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}
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uint8_t bcd2dec(uint8_t b)
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{
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return ((b/16 * 10) + (b % 16));
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}
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uint8_t rtc_read_byte(uint8_t offset)
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{
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2020-05-15 11:50:11 +02:00
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i2c_t::start<RTC_ADDR>(false);
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i2c_t::write(offset);
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i2c_t::stop();
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i2c_t::start<RTC_ADDR>(true);
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const auto received = i2c_t::read<true>();
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i2c_t::stop();
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2017-04-27 00:05:38 +02:00
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2020-05-15 11:50:11 +02:00
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return received;
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2017-04-27 00:05:38 +02:00
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}
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void rtc_write_byte(uint8_t b, uint8_t offset)
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{
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2020-05-15 11:50:11 +02:00
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i2c_t::start<RTC_ADDR>(false);
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i2c_t::write(offset);
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i2c_t::write(b);
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i2c_t::stop();
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2017-04-27 00:05:38 +02:00
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}
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static bool s_is_ds1307 = false;
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static bool s_is_ds3231 = false;
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void rtc_init(void)
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{
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2020-05-15 11:50:11 +02:00
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i2c_t::init();
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2017-04-27 00:05:38 +02:00
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// Attempt autodetection:
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// 1) Read and save temperature register
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// 2) Write a value to temperature register
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// 3) Read back the value
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// equal to the one written: DS1307, write back saved value and return
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// different from written: DS3231
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2020-05-15 11:50:11 +02:00
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2017-04-27 00:05:38 +02:00
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uint8_t temp1 = rtc_read_byte(0x11);
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uint8_t temp2 = rtc_read_byte(0x12);
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2020-05-15 11:50:11 +02:00
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2017-04-27 00:05:38 +02:00
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rtc_write_byte(0xee, 0x11);
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rtc_write_byte(0xdd, 0x12);
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if (rtc_read_byte(0x11) == 0xee && rtc_read_byte(0x12) == 0xdd) {
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s_is_ds1307 = true;
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// restore values
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rtc_write_byte(temp1, 0x11);
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rtc_write_byte(temp2, 0x12);
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}
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else {
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s_is_ds3231 = true;
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}
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}
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// Autodetection
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bool rtc_is_ds1307(void) { return s_is_ds1307; }
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bool rtc_is_ds3231(void) { return s_is_ds3231; }
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// Autodetection override
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void rtc_set_ds1307(void) { s_is_ds1307 = true; s_is_ds3231 = false; }
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void rtc_set_ds3231(void) { s_is_ds1307 = false; s_is_ds3231 = true; }
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2017-12-16 19:48:54 +01:00
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struct rtc_tm* rtc_get_time(void)
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2017-04-27 00:05:38 +02:00
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{
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uint8_t rtc[9];
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uint8_t century = 0;
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// read 7 bytes starting from register 0
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// sec, min, hour, day-of-week, date, month, year
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2020-05-15 11:50:11 +02:00
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i2c_t::start<RTC_ADDR>(false);
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i2c_t::write(0x0);
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i2c_t::stop();
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2017-04-27 00:05:38 +02:00
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2020-05-15 11:50:11 +02:00
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i2c_t::start<RTC_ADDR>(true);
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i2c_t::readBytes<7>(rtc);
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i2c_t::stop();
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2017-04-27 00:05:38 +02:00
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// Clear clock halt bit from read data
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// This starts the clock for a DS1307, and has no effect for a DS3231
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rtc[0] &= ~(_BV(CH_BIT)); // clear bit
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2017-12-16 19:48:54 +01:00
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_rtc_tm.sec = bcd2dec(rtc[0]);
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_rtc_tm.min = bcd2dec(rtc[1]);
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_rtc_tm.hour = bcd2dec(rtc[2]);
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_rtc_tm.mday = bcd2dec(rtc[4]);
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_rtc_tm.mon = bcd2dec(rtc[5] & 0x1F); // returns 1-12
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2017-04-27 00:05:38 +02:00
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century = (rtc[5] & 0x80) >> 7;
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2017-12-16 19:48:54 +01:00
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_rtc_tm.year = century == 1 ? 2000 + bcd2dec(rtc[6]) : 1900 + bcd2dec(rtc[6]); // year 0-99
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_rtc_tm.wday = bcd2dec(rtc[3]); // returns 1-7
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if (_rtc_tm.hour == 0) {
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_rtc_tm.twelveHour = 0;
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_rtc_tm.am = 1;
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} else if (_rtc_tm.hour < 12) {
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_rtc_tm.twelveHour = _rtc_tm.hour;
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_rtc_tm.am = 1;
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2017-04-27 00:05:38 +02:00
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} else {
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2017-12-16 19:48:54 +01:00
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_rtc_tm.twelveHour = _rtc_tm.hour - 12;
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_rtc_tm.am = 0;
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2017-04-27 00:05:38 +02:00
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}
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2017-12-16 19:48:54 +01:00
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return &_rtc_tm;
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2017-04-27 00:05:38 +02:00
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}
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void rtc_get_time_s(uint8_t* hour, uint8_t* min, uint8_t* sec)
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{
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uint8_t rtc[9];
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// read 7 bytes starting from register 0
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// sec, min, hour, day-of-week, date, month, year
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2020-05-15 11:50:11 +02:00
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i2c_t::start<RTC_ADDR>(false);
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i2c_t::write(0x0);
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i2c_t::stop();
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i2c_t::start<RTC_ADDR>(true);
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i2c_t::readBytes<7>(rtc);
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i2c_t::stop();
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2017-04-27 00:05:38 +02:00
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if (sec) *sec = bcd2dec(rtc[0]);
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if (min) *min = bcd2dec(rtc[1]);
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if (hour) *hour = bcd2dec(rtc[2]);
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}
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// fixme: support 12-hour mode for setting time
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2017-12-16 19:48:54 +01:00
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void rtc_set_time(struct rtc_tm* tm_)
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2017-04-27 00:05:38 +02:00
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{
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2020-05-15 11:50:11 +02:00
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i2c_t::start<RTC_ADDR>(false);
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i2c_t::write(0x0);
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2017-04-27 00:05:38 +02:00
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uint8_t century;
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if (tm_->year > 2000) {
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century = 0x80;
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tm_->year = tm_->year - 2000;
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} else {
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century = 0;
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tm_->year = tm_->year - 1900;
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}
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// clock halt bit is 7th bit of seconds: this is always cleared to start the clock
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2020-05-15 11:50:11 +02:00
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i2c_t::write(dec2bcd(tm_->sec)); // seconds
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i2c_t::write(dec2bcd(tm_->min)); // minutes
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i2c_t::write(dec2bcd(tm_->hour)); // hours
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i2c_t::write(dec2bcd(tm_->wday)); // day of week
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i2c_t::write(dec2bcd(tm_->mday)); // day
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i2c_t::write(dec2bcd(tm_->mon) + century); // month
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i2c_t::write(dec2bcd(tm_->year)); // year
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i2c_t::stop();
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2017-04-27 00:05:38 +02:00
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}
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void rtc_set_time_s(uint8_t hour, uint8_t min, uint8_t sec)
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{
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2020-05-15 11:50:11 +02:00
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i2c_t::start<RTC_ADDR>(false);
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i2c_t::write(0x0);
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2017-04-27 00:05:38 +02:00
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// clock halt bit is 7th bit of seconds: this is always cleared to start the clock
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2020-05-15 11:50:11 +02:00
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i2c_t::write(dec2bcd(sec)); // seconds
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i2c_t::write(dec2bcd(min)); // minutes
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i2c_t::write(dec2bcd(hour)); // hours
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i2c_t::stop();
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2017-04-27 00:05:38 +02:00
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}
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// DS1307 only (has no effect when run on DS3231)
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// halt/start the clock
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// 7th bit of register 0 (second register)
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// 0 = clock is running
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// 1 = clock is not running
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void rtc_run_clock(bool run)
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{
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if (s_is_ds3231) return;
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2020-05-15 11:50:11 +02:00
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2017-04-27 00:05:38 +02:00
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uint8_t b = rtc_read_byte(0x0);
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if (run)
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b &= ~(_BV(CH_BIT)); // clear bit
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else
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b |= _BV(CH_BIT); // set bit
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2020-05-15 11:50:11 +02:00
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2020-05-15 09:25:48 +02:00
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rtc_write_byte(b, 0x0);
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2017-04-27 00:05:38 +02:00
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}
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// DS1307 only
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// Returns true if the clock is running, false otherwise
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// For DS3231, it always returns true
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bool rtc_is_clock_running(void)
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{
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if (s_is_ds3231) return true;
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2020-05-15 11:50:11 +02:00
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2017-04-27 00:05:38 +02:00
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uint8_t b = rtc_read_byte(0x0);
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if (b & _BV(CH_BIT)) return false;
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return true;
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}
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void ds3231_get_temp_int(int8_t* i, uint8_t* f)
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{
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uint8_t msb, lsb;
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2020-05-15 11:50:11 +02:00
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2017-04-27 00:05:38 +02:00
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*i = 0;
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*f = 0;
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2020-05-15 11:50:11 +02:00
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2017-04-27 00:05:38 +02:00
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if (s_is_ds1307) return; // only valid on DS3231
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2020-05-15 11:50:11 +02:00
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i2c_t::start<RTC_ADDR>(false);
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2017-04-27 00:05:38 +02:00
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// temp registers 0x11 and 0x12
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2020-05-15 11:50:11 +02:00
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i2c_t::write(0x11);
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i2c_t::stop();
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i2c_t::start<RTC_ADDR>(true);
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msb = i2c_t::read(); // integer part (in twos complement)
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lsb = i2c_t::read<true>(); // fraction part
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// integer part in entire byte
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*i = msb;
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// fractional part in top two bits (increments of 0.25)
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*f = (lsb >> 6) * 25;
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// float value can be read like so:
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// float temp = ((((short)msb << 8) | (short)lsb) >> 6) / 4.0f;
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2017-04-27 00:05:38 +02:00
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}
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void rtc_force_temp_conversion(uint8_t block)
|
|
|
|
{
|
|
|
|
if (s_is_ds1307) return; // only valid on DS3231
|
|
|
|
|
|
|
|
// read control register (0x0E)
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x0E);
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(true);
|
|
|
|
uint8_t ctrl = i2c_t::read<true>();
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
ctrl |= 0b00100000; // Set CONV bit
|
|
|
|
|
|
|
|
// write new control register value
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x0E);
|
|
|
|
i2c_t::write(ctrl);
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
if (!block) return;
|
2020-05-15 11:50:11 +02:00
|
|
|
|
2017-04-27 00:05:38 +02:00
|
|
|
// Temp conversion is ready when control register becomes 0
|
|
|
|
do {
|
|
|
|
// Block until CONV is 0
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x0E);
|
|
|
|
i2c_t::stop();
|
|
|
|
|
|
|
|
i2c_t::start<RTC_ADDR>(true);
|
|
|
|
// HACK: Missing stop after read, might still work though
|
|
|
|
} while ((i2c_t::read<true>() & 0b00100000) != 0);
|
2017-04-27 00:05:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#define DS1307_SRAM_ADDR 0x08
|
|
|
|
|
|
|
|
// SRAM: 56 bytes from address 0x08 to 0x3f (DS1307-only)
|
|
|
|
void rtc_get_sram(uint8_t* data)
|
|
|
|
{
|
|
|
|
// cannot receive 56 bytes in one go, because of the TWI library buffer limit
|
|
|
|
// so just receive one at a time for simplicity
|
|
|
|
for(int i=0;i<56;i++)
|
|
|
|
data[i] = rtc_get_sram_byte(i);
|
|
|
|
}
|
|
|
|
|
|
|
|
void rtc_set_sram(uint8_t *data)
|
|
|
|
{
|
|
|
|
// cannot send 56 bytes in one go, because of the TWI library buffer limit
|
|
|
|
// so just send one at a time for simplicity
|
|
|
|
for(int i=0;i<56;i++)
|
|
|
|
rtc_set_sram_byte(data[i], i);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t rtc_get_sram_byte(uint8_t offset)
|
|
|
|
{
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(DS1307_SRAM_ADDR + offset);
|
|
|
|
i2c_t::stop();
|
|
|
|
|
|
|
|
i2c_t::start<RTC_ADDR>(true);
|
|
|
|
const auto received = i2c_t::read<true>();
|
|
|
|
i2c_t::stop();
|
|
|
|
return received;
|
2017-04-27 00:05:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void rtc_set_sram_byte(uint8_t b, uint8_t offset)
|
|
|
|
{
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(DS1307_SRAM_ADDR + offset);
|
|
|
|
i2c_t::write(b);
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void rtc_SQW_enable(bool enable)
|
|
|
|
{
|
|
|
|
if (s_is_ds1307) {
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x07);
|
|
|
|
i2c_t::stop();
|
|
|
|
|
2017-04-27 00:05:38 +02:00
|
|
|
// read control
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(true);
|
|
|
|
uint8_t control = i2c_t::read<true>();
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
if (enable)
|
|
|
|
control |= 0b00010000; // set SQWE to 1
|
|
|
|
else
|
|
|
|
control &= ~0b00010000; // set SQWE to 0
|
|
|
|
|
|
|
|
// write control back
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x07);
|
|
|
|
i2c_t::write(control);
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
}
|
|
|
|
else { // DS3231
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x0E);
|
|
|
|
i2c_t::stop();
|
|
|
|
|
2017-04-27 00:05:38 +02:00
|
|
|
// read control
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(true);
|
|
|
|
uint8_t control = i2c_t::read<true>();
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
if (enable) {
|
|
|
|
control |= 0b01000000; // set BBSQW to 1
|
|
|
|
control &= ~0b00000100; // set INTCN to 0
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
control &= ~0b01000000; // set BBSQW to 0
|
|
|
|
}
|
|
|
|
|
|
|
|
// write control back
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x0E);
|
|
|
|
i2c_t::write(control);
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void rtc_SQW_set_freq(enum RTC_SQW_FREQ freq)
|
|
|
|
{
|
|
|
|
if (s_is_ds1307) {
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x07);
|
|
|
|
i2c_t::stop();
|
|
|
|
|
2017-04-27 00:05:38 +02:00
|
|
|
// read control (uses bits 0 and 1)
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(true);
|
|
|
|
uint8_t control = i2c_t::read<true>();
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
control &= ~0b00000011; // Set to 0
|
|
|
|
control |= freq; // Set freq bitmask
|
|
|
|
|
|
|
|
// write control back
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x07);
|
|
|
|
i2c_t::write(control);
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
}
|
|
|
|
else { // DS3231
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x0E);
|
|
|
|
i2c_t::stop();
|
|
|
|
|
2017-04-27 00:05:38 +02:00
|
|
|
// read control (uses bits 3 and 4)
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(true);
|
|
|
|
uint8_t control = i2c_t::read<true>();
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
control &= ~0b00011000; // Set to 0
|
|
|
|
control |= (freq << 4); // Set freq bitmask
|
|
|
|
|
|
|
|
// write control back
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x0E);
|
|
|
|
i2c_t::write(control);
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void rtc_osc32kHz_enable(bool enable)
|
|
|
|
{
|
|
|
|
if (!s_is_ds3231) return;
|
|
|
|
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x0F);
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
// read status
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(true);
|
|
|
|
uint8_t status = i2c_t::read<true>();
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
|
|
|
|
if (enable)
|
|
|
|
status |= 0b00001000; // set to 1
|
|
|
|
else
|
|
|
|
status &= ~0b00001000; // Set to 0
|
|
|
|
|
|
|
|
// write status back
|
2020-05-15 11:50:11 +02:00
|
|
|
i2c_t::start<RTC_ADDR>(false);
|
|
|
|
i2c_t::write(0x0F);
|
|
|
|
i2c_t::write(status);
|
|
|
|
i2c_t::stop();
|
2017-04-27 00:05:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// Alarm functionality
|
2020-05-15 11:50:11 +02:00
|
|
|
// fixme: should decide if "alarm disabled" mode should be available, or if alarm should always be enabled
|
2017-04-27 00:05:38 +02:00
|
|
|
// at 00:00:00. Currently, "alarm disabled" only works for ds3231
|
|
|
|
void rtc_reset_alarm(void)
|
|
|
|
{
|
|
|
|
if (s_is_ds1307) {
|
|
|
|
rtc_set_sram_byte(0, 0); // hour
|
|
|
|
rtc_set_sram_byte(0, 1); // minute
|
|
|
|
rtc_set_sram_byte(0, 2); // second
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
// writing 0 to bit 7 of all four alarm 1 registers disables alarm
|
|
|
|
rtc_write_byte(0, 0x07); // second
|
|
|
|
rtc_write_byte(0, 0x08); // minute
|
|
|
|
rtc_write_byte(0, 0x09); // hour
|
|
|
|
rtc_write_byte(0, 0x0a); // day
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// fixme: add an option to set whether or not the INTCN and Interrupt Enable flag is set when setting the alarm
|
|
|
|
void rtc_set_alarm_s(uint8_t hour, uint8_t min, uint8_t sec)
|
|
|
|
{
|
|
|
|
if (hour > 23) return;
|
|
|
|
if (min > 59) return;
|
|
|
|
if (sec > 59) return;
|
|
|
|
|
|
|
|
if (s_is_ds1307) {
|
|
|
|
rtc_set_sram_byte(hour, 0); // hour
|
|
|
|
rtc_set_sram_byte(min, 1); // minute
|
|
|
|
rtc_set_sram_byte(sec, 2); // second
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
/*
|
|
|
|
* 07h: A1M1:0 Alarm 1 seconds
|
|
|
|
* 08h: A1M2:0 Alarm 1 minutes
|
|
|
|
* 09h: A1M3:0 Alarm 1 hour (bit6 is am/pm flag in 12h mode)
|
|
|
|
* 0ah: A1M4:1 Alarm 1 day/date (bit6: 1 for day, 0 for date)
|
|
|
|
* Sets alarm to fire when hour, minute and second matches
|
|
|
|
*/
|
|
|
|
rtc_write_byte(dec2bcd(sec), 0x07); // second
|
|
|
|
rtc_write_byte(dec2bcd(min), 0x08); // minute
|
|
|
|
rtc_write_byte(dec2bcd(hour), 0x09); // hour
|
|
|
|
rtc_write_byte(0b10000001, 0x0a); // day (upper bit must be set)
|
|
|
|
|
|
|
|
// clear alarm flag
|
|
|
|
uint8_t val = rtc_read_byte(0x0f);
|
|
|
|
rtc_write_byte(val & ~0b00000001, 0x0f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-12-16 19:48:54 +01:00
|
|
|
void rtc_set_alarm(struct rtc_tm* tm_)
|
2017-04-27 00:05:38 +02:00
|
|
|
{
|
|
|
|
if (!tm_) return;
|
|
|
|
rtc_set_alarm_s(tm_->hour, tm_->min, tm_->sec);
|
|
|
|
}
|
|
|
|
|
|
|
|
void rtc_get_alarm_s(uint8_t* hour, uint8_t* min, uint8_t* sec)
|
|
|
|
{
|
|
|
|
if (s_is_ds1307) {
|
|
|
|
if (hour) *hour = rtc_get_sram_byte(0);
|
|
|
|
if (min) *min = rtc_get_sram_byte(1);
|
|
|
|
if (sec) *sec = rtc_get_sram_byte(2);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
*sec = bcd2dec(rtc_read_byte(0x07) & ~0b10000000);
|
|
|
|
*min = bcd2dec(rtc_read_byte(0x08) & ~0b10000000);
|
|
|
|
*hour = bcd2dec(rtc_read_byte(0x09) & ~0b10000000);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-12-16 19:48:54 +01:00
|
|
|
struct rtc_tm* rtc_get_alarm(void)
|
2017-04-27 00:05:38 +02:00
|
|
|
{
|
|
|
|
uint8_t hour, min, sec;
|
|
|
|
|
|
|
|
rtc_get_alarm_s(&hour, &min, &sec);
|
2017-12-16 19:48:54 +01:00
|
|
|
_rtc_tm.hour = hour;
|
|
|
|
_rtc_tm.min = min;
|
|
|
|
_rtc_tm.sec = sec;
|
|
|
|
return &_rtc_tm;
|
2017-04-27 00:05:38 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool rtc_check_alarm(void)
|
|
|
|
{
|
|
|
|
if (s_is_ds1307) {
|
|
|
|
uint8_t hour = rtc_get_sram_byte(0);
|
|
|
|
uint8_t min = rtc_get_sram_byte(1);
|
|
|
|
uint8_t sec = rtc_get_sram_byte(2);
|
|
|
|
|
|
|
|
uint8_t cur_hour, cur_min, cur_sec;
|
|
|
|
rtc_get_time_s(&cur_hour, &cur_min, &cur_sec);
|
2020-05-15 11:50:11 +02:00
|
|
|
|
2017-04-27 00:05:38 +02:00
|
|
|
if (cur_hour == hour && cur_min == min && cur_sec == sec)
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
// Alarm 1 flag (A1F) in bit 0
|
|
|
|
uint8_t val = rtc_read_byte(0x0f);
|
|
|
|
|
|
|
|
// clear flag when set
|
|
|
|
if (val & 1)
|
|
|
|
rtc_write_byte(val & ~0b00000001, 0x0f);
|
2020-05-15 11:50:11 +02:00
|
|
|
|
2017-04-27 00:05:38 +02:00
|
|
|
return val & 1 ? 1 : 0;
|
|
|
|
}
|
|
|
|
}
|