Cancel the GPIO bridge's cycle timers with the state they drive: avr_reset drops the TX latch, whose falling edge starts a spurious decode before bridge_reset runs, and the stale sampler then interleaves with the loader's first real answer through the shared shift state — the first post-reset replies came back corrupted and the knock retries burned the activation window into the application. Wrap the mega's registered flash ioctl to re-dispatch page erases with Z masked to the page boundary: simavr's PGERS handler erases spm_pagesize bytes from Z & ~1 (its PGWRT path masks correctly), wiping the neighbouring page when Z sits past the page start, which hardware permits (§26.8.1). Model the write-once temporary buffer in the tiny NVM module — silicon refuses a second load per word until the buffer clears, and a last-write- wins model masks real firmware bugs. Optional arguments select the reset vector (the mega's fuse profiles) and a raw flash image to resume from (power-fail tests re-enter a dumped state). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
391 lines
12 KiB
C
391 lines
12 KiB
C
// simavr "device" for the pureboot protocol tests, all three chips. Loads
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// the boot-linked ELF at the loader base, starts execution there (BOOTRST /
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// the patched vector are not what is under test), and exposes the loader's
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// serial link as a pty for the real host tool:
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//
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// - ATmega328P: the hardware USART0 through simavr's uart_pty.
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// - Tinies: an 8N1 bridge between a pty and the GPIO software UART
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// (drives PB0, the loader's RX; decodes PB1, its TX), timed against the
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// simulated cycle counter.
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//
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// simavr's tiny cores decode the SPM opcode but attach no NVM module — SPM
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// is a silent no-op (the mega's boot section has one, avr_flash). The
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// missing module is supplied here: the SPM ioctl reads SPMCSR/Z/r1:r0 and
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// implements buffer fill, page erase, page write, and CTPB, completing
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// instantly. RFLB's LPM diversion (fuse readout) stays unmodeled, so the
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// 'F' command answers with flash bytes — the tests assert transport only.
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//
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// On exit (or SIGTERM) the flash and EEPROM are dumped to files for a
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// ground-truth cross-check against what the host read back.
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#include <fcntl.h>
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#include <pty.h>
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#include <signal.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <termios.h>
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#include <unistd.h>
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#include "avr_eeprom.h"
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#include "avr_flash.h"
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#include "avr_ioport.h"
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#include "avr_uart.h"
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#include "sim_avr.h"
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#include "sim_elf.h"
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#include "sim_io.h"
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#include "uart_pty.h"
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static avr_t *avr;
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static uart_pty_t uart_pty;
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static int use_uart_pty;
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static const char *dump_path;
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static uint32_t reset_pc;
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static volatile sig_atomic_t reset_requested;
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// simavr 1.6's avr_flash PGERS handler erases spm_pagesize bytes starting at
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// Z & ~1 instead of the page containing Z (its PGWRT path masks correctly) —
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// hardware ignores the in-page bits (§26.8.1), so an erase issued with Z
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// anywhere inside the page wipes half the neighbouring page in simulation
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// only. Wrap the mega's registered flash ioctl and re-dispatch page erases
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// with Z forced to the page boundary; everything else passes through.
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static avr_flash_t *mega_flash;
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static int (*mega_flash_ioctl)(avr_io_t *io, uint32_t ctl, void *param);
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static int fixed_flash_ioctl(avr_io_t *io, uint32_t ctl, void *param)
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{
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if (ctl == AVR_IOCTL_FLASH_SPM && avr_regbit_get(io->avr, mega_flash->pgers)) {
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uint16_t z = (uint16_t)(io->avr->data[30] | (io->avr->data[31] << 8));
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uint16_t masked = (uint16_t)(z & ~(mega_flash->spm_pagesize - 1));
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io->avr->data[30] = (uint8_t)masked;
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io->avr->data[31] = (uint8_t)(masked >> 8);
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int result = mega_flash_ioctl(io, ctl, param);
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io->avr->data[30] = (uint8_t)z;
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io->avr->data[31] = (uint8_t)(z >> 8);
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return result;
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}
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return mega_flash_ioctl(io, ctl, param);
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}
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static void fix_mega_flash_erase(void)
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{
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for (avr_io_t *io = avr->io_port; io; io = io->next) {
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if (io->kind && strcmp(io->kind, "flash") == 0) {
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mega_flash = (avr_flash_t *)io;
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mega_flash_ioctl = io->ioctl;
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io->ioctl = fixed_flash_ioctl;
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return;
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}
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}
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fprintf(stderr, "device: no flash module to fix — SPM page erases may misalign\n");
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}
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static void request_reset(int sig)
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{
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(void)sig;
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reset_requested = 1;
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}
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// ------------------------------------------------------------- tiny NVM ---
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typedef struct {
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avr_io_t io;
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uint8_t buffer[128];
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uint8_t used[128]; // a buffer word loads once until erased — like silicon
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unsigned page;
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} tiny_nvm_t;
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static tiny_nvm_t nvm;
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static int nvm_ioctl(avr_io_t *io, uint32_t ctl, void *param)
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{
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(void)param;
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if (ctl != AVR_IOCTL_FLASH_SPM)
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return -1;
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tiny_nvm_t *n = (tiny_nvm_t *)io;
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avr_t *mcu = io->avr;
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uint8_t command = mcu->data[0x57] & 0x1f; // SPMCSR, both tinies
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uint16_t z = (uint16_t)(mcu->data[30] | (mcu->data[31] << 8));
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uint32_t page_base = (uint32_t)(z & ~(n->page - 1)) % (mcu->flashend + 1);
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if (command == 0x01) { // SPMEN alone: buffer fill from r1:r0
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unsigned offset = z & (n->page - 1) & ~1u;
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if (!n->used[offset]) { // first write wins until the buffer clears
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n->buffer[offset] = mcu->data[0];
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n->buffer[offset + 1] = mcu->data[1];
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n->used[offset] = 1;
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}
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} else if (command == 0x03) { // PGERS
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memset(mcu->flash + page_base, 0xff, n->page);
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} else if (command == 0x05) { // PGWRT: programming only clears bits
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for (unsigned i = 0; i < n->page; i++)
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mcu->flash[page_base + i] &= n->buffer[i];
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memset(n->buffer, 0xff, n->page);
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memset(n->used, 0, n->page);
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} else if (command == 0x11) { // CTPB
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memset(n->buffer, 0xff, n->page);
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memset(n->used, 0, n->page);
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}
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mcu->data[0x57] &= (uint8_t)~0x1f; // the operation completes instantly
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return 0;
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}
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// ----------------------------------------------------------- GPIO bridge ---
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static int pty_master = -1;
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static avr_irq_t *rx_pin; // the loader's RX (PB0), driven from the pty
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static avr_cycle_count_t bit_cycles;
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static int tx_level = 1, tx_active, tx_bit;
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static uint8_t tx_shift;
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static avr_cycle_count_t tx_sample(avr_t *mcu, avr_cycle_count_t when, void *param)
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{
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(void)mcu;
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(void)param;
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tx_shift = (uint8_t)((tx_shift >> 1) | (tx_level ? 0x80 : 0));
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if (++tx_bit < 8)
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return when + bit_cycles;
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if (write(pty_master, &tx_shift, 1) != 1)
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fprintf(stderr, "device: pty write lost a byte\n");
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tx_active = 0;
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return 0;
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}
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static void tx_hook(avr_irq_t *irq, uint32_t value, void *param)
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{
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(void)irq;
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(void)param;
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int level = value & 1;
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if (!tx_active && tx_level == 1 && level == 0) { // start edge
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tx_active = 1;
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tx_bit = 0;
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avr_cycle_timer_register(avr, bit_cycles + bit_cycles / 2, tx_sample, NULL);
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}
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tx_level = level;
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}
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static uint8_t rx_queue[8192];
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static unsigned rx_head, rx_tail; // ring: head = next to send
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static int rx_active, rx_bit;
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static uint8_t rx_byte;
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static void rx_start_next(void);
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static avr_cycle_count_t rx_step(avr_t *mcu, avr_cycle_count_t when, void *param)
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{
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(void)mcu;
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(void)param;
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if (rx_bit < 8) {
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avr_raise_irq(rx_pin, (rx_byte >> rx_bit) & 1);
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rx_bit++;
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return when + bit_cycles;
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}
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if (rx_bit == 8) { // stop bit, plus one idle bit of margin
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avr_raise_irq(rx_pin, 1);
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rx_bit++;
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return when + 2 * bit_cycles;
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}
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rx_active = 0;
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rx_start_next();
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return 0;
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}
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static void rx_start_next(void)
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{
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if (rx_active || rx_head == rx_tail)
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return;
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rx_byte = rx_queue[rx_head];
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rx_head = (rx_head + 1) % sizeof(rx_queue);
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rx_active = 1;
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rx_bit = 0;
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avr_raise_irq(rx_pin, 0); // start bit
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avr_cycle_timer_register(avr, bit_cycles, rx_step, NULL);
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}
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// A reset abandons whatever the bridge was mid-transfer: bytes still queued
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// for a chip that no longer has the context to receive them meaningfully,
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// and a decode in progress on a TX line the reset may have already changed.
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// The pending cycle timers must go with the state: avr_reset drops the TX
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// output latch, whose falling edge starts a spurious decode before this
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// runs, and a stale tx_sample would then interleave with the loader's first
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// real answer through the shared shift state, corrupting it.
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static void bridge_reset(void)
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{
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avr_cycle_timer_cancel(avr, tx_sample, NULL);
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avr_cycle_timer_cancel(avr, rx_step, NULL);
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rx_head = rx_tail = 0;
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rx_active = 0;
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tx_active = 0;
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tx_level = 1;
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avr_raise_irq(rx_pin, 1); // idle line
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}
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static void poll_pty(void)
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{
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uint8_t chunk[256];
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ssize_t got = read(pty_master, chunk, sizeof(chunk));
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for (ssize_t i = 0; i < got; i++) {
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unsigned next = (rx_tail + 1) % sizeof(rx_queue);
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if (next == rx_head)
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break; // full: the host will retry on timeout
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rx_queue[rx_tail] = chunk[i];
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rx_tail = next;
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}
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if (got > 0)
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rx_start_next();
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}
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// ------------------------------------------------------------------ main ---
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static void finish(int sig)
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{
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(void)sig;
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if (dump_path) {
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FILE *f = fopen(dump_path, "wb");
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if (f) {
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fwrite(avr->flash, 1, avr->flashend + 1, f);
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fclose(f);
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}
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avr_eeprom_desc_t ee = {.ee = NULL, .offset = 0, .size = 0};
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if (avr_ioctl(avr, AVR_IOCTL_EEPROM_GET, &ee) == 0 && ee.ee && ee.size) {
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char path[512];
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snprintf(path, sizeof(path), "%s.eeprom", dump_path);
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f = fopen(path, "wb");
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if (f) {
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fwrite(ee.ee, 1, ee.size, f);
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fclose(f);
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}
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}
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}
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if (use_uart_pty)
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uart_pty_stop(&uart_pty);
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_exit(0);
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}
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int main(int argc, char *argv[])
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{
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if (argc < 8 || argc > 10) {
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fprintf(stderr,
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"usage: %s <pureboot.elf> <mcu> <hz> <base_hex> <page> <baud> <flash_dump>"
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" [reset_hex] [resume_flash]\n"
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" reset_hex: reset vector (default: base on the mega, 0 on the tinies)\n"
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" resume_flash: raw full-flash image loaded instead of the ELF — a prior\n"
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" run's dump, for power-fail resume tests\n",
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argv[0]);
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return 2;
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}
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const char *mcu_name = argv[2];
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uint32_t base = (uint32_t)strtoul(argv[4], NULL, 0);
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unsigned page = (unsigned)atoi(argv[5]);
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unsigned baud = (unsigned)atoi(argv[6]);
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dump_path = argv[7];
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use_uart_pty = strcmp(mcu_name, "atmega328p") == 0;
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avr = avr_make_mcu_by_name(mcu_name);
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if (!avr) {
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fprintf(stderr, "device: no %s core\n", mcu_name);
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return 1;
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}
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avr_init(avr);
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avr->frequency = (uint32_t)strtoul(argv[3], NULL, 0);
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memset(avr->flash, 0xff, avr->flashend + 1); // real flash powers up erased
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if (argc > 9) {
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// Resume: the full flash image of an interrupted prior run.
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FILE *f = fopen(argv[9], "rb");
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if (!f || fread(avr->flash, 1, avr->flashend + 1, f) == 0) {
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fprintf(stderr, "device: cannot read %s\n", argv[9]);
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return 1;
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}
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fclose(f);
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} else {
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elf_firmware_t fw = {0};
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if (elf_read_firmware(argv[1], &fw) != 0) {
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fprintf(stderr, "device: cannot read %s\n", argv[1]);
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return 1;
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}
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memcpy(avr->flash + base, fw.flash, fw.flashsize);
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}
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// The mega enters the loader in hardware (BOOTRST, not modeled — the
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// argument picks the modeled fuse's target); the tinies reset to word 0
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// like silicon — erased flash walks up into the loader, and after the
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// host's surgery the patched vector routes there.
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reset_pc = argc > 8 ? (uint32_t)strtoul(argv[8], NULL, 0) : (use_uart_pty ? base : 0);
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avr->pc = reset_pc;
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avr->codeend = avr->flashend;
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// Erased EEPROM, as hardware powers up (simavr zeroes it).
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uint8_t blank[1024];
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memset(blank, 0xff, sizeof(blank));
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avr_eeprom_desc_t seed = {.ee = blank, .offset = 0, .size = 0};
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if (avr_ioctl(avr, AVR_IOCTL_EEPROM_GET, &seed) == 0 && seed.size <= sizeof(blank)) {
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seed.ee = blank;
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avr_ioctl(avr, AVR_IOCTL_EEPROM_SET, &seed);
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}
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if (use_uart_pty) {
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fix_mega_flash_erase();
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// POLL_SLEEP paces an idle-polling loader in host real time (a
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// no-hardware CPU-saving hack); clear it so cycles run free.
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uint32_t flags = 0;
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avr_ioctl(avr, AVR_IOCTL_UART_GET_FLAGS('0'), &flags);
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flags &= ~AVR_UART_FLAG_POLL_SLEEP;
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avr_ioctl(avr, AVR_IOCTL_UART_SET_FLAGS('0'), &flags);
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uart_pty_init(avr, &uart_pty);
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uart_pty_connect(&uart_pty, '0');
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printf("PB_PTY %s\n", uart_pty.pty.slavename);
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} else {
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nvm.page = page;
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memset(nvm.buffer, 0xff, sizeof(nvm.buffer));
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nvm.io.kind = "tiny_nvm";
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nvm.io.ioctl = nvm_ioctl;
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avr_register_io(avr, &nvm.io);
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bit_cycles = (avr->frequency + baud / 2) / baud; // matches uart.hpp's own rounding exactly
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rx_pin = avr_io_getirq(avr, AVR_IOCTL_IOPORT_GETIRQ('B'), 0);
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avr_irq_register_notify(avr_io_getirq(avr, AVR_IOCTL_IOPORT_GETIRQ('B'), 1), tx_hook, NULL);
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avr_raise_irq(rx_pin, 1); // idle line
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int slave;
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struct termios raw;
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cfmakeraw(&raw);
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if (openpty(&pty_master, &slave, NULL, &raw, NULL) != 0) {
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fprintf(stderr, "device: openpty failed\n");
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return 1;
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}
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fcntl(pty_master, F_SETFL, O_NONBLOCK);
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printf("PB_PTY %s\n", ttyname(slave));
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}
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fflush(stdout);
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signal(SIGTERM, finish);
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signal(SIGINT, finish);
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signal(SIGUSR1, request_reset); // an external reset line, for the tests
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long since_poll = 0;
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for (;;) {
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int state = avr_run(avr);
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if (state == cpu_Done || state == cpu_Crashed)
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break;
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if (reset_requested) {
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reset_requested = 0;
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avr_reset(avr);
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avr->pc = reset_pc;
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if (use_uart_pty) { // reset restores the pacing hack; re-clear it
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uint32_t flags = 0;
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avr_ioctl(avr, AVR_IOCTL_UART_GET_FLAGS('0'), &flags);
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flags &= ~AVR_UART_FLAG_POLL_SLEEP;
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avr_ioctl(avr, AVR_IOCTL_UART_SET_FLAGS('0'), &flags);
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} else {
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bridge_reset();
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}
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}
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if (!use_uart_pty && ++since_poll >= 2000) {
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since_poll = 0;
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poll_pty();
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}
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}
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finish(0);
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return 0;
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}
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