BlackMark
14efef96cc
pureboot.py --autobaud sends the 0xC0 calibration pulse and a single knock at the host's chosen baud, reads the slimmed info block, and derives the full geometry from the signature (AUTOBAUD_GEOMETRY, a table over every pureboot chip). Everything downstream — flash, EEPROM, fuses, hand-over, verify — is the fixed-baud path unchanged; the dropped write guard is host-transparent. test/pbautobaud.py drives each variant over the GPIO⇄pty software-UART bridge through the calibration handshake and a flash + EEPROM + fuse round-trip cross-checked against the simulator's ground-truth memory, then repeats at double the F_CPU with the same binary — the clock-agnostic property autobaud exists for. Wired as pureboot.autobaud_pure/reg on the near-flash 328P and the word-addressed 1284P. A wrong measured unit fails the flash/verify, so the test also pins the codegen-coupled calibration constant against a toolchain bump. Both variants green in sim on both chips at two clocks each; the fixed-baud suite is unaffected. Only real-hardware acceptance on an RC part remains (pureboot/autobaud.md). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
418 lines
22 KiB
CMake
418 lines
22 KiB
CMake
cmake_minimum_required(VERSION 3.28)
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project(tsb_libavr LANGUAGES CXX)
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# libavr from a local checkout (LIBAVR_ROOT) or the forge; the toolchain file
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# comes from the same checkout via CMakePresets.json.
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include(FetchContent)
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if(NOT LIBAVR_ROOT AND DEFINED ENV{LIBAVR_ROOT})
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set(LIBAVR_ROOT $ENV{LIBAVR_ROOT})
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endif()
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if(LIBAVR_ROOT)
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FetchContent_Declare(libavr SOURCE_DIR ${LIBAVR_ROOT})
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else()
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FetchContent_Declare(libavr GIT_REPOSITORY git@git.blackmark.me:avr/libavr.git GIT_TAG main)
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endif()
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FetchContent_MakeAvailable(libavr)
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if(PROJECT_IS_TOP_LEVEL)
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add_compile_options(-Werror) # warnings are errors for the port's own code
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enable_testing()
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# The behavioral tests drive the real wire protocols over a simavr pty
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# (as the host tools do) and actually flash the device. The runners are
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# host programs built at configure time against libsimavr; if they or
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# Python are missing, only the size tests run.
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find_program(_host_cc NAMES cc gcc)
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find_package(Python3 COMPONENTS Interpreter)
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if(_host_cc AND Python3_FOUND)
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set(PB_DEVICE ${CMAKE_BINARY_DIR}/pureboot_device)
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execute_process(
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COMMAND ${_host_cc} -O2 -I/usr/include/simavr -I/usr/include/simavr/parts
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-o ${PB_DEVICE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pureboot_device.c
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-lsimavr -lsimavrparts -lelf -lutil
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RESULT_VARIABLE _pbdev_res ERROR_VARIABLE _pbdev_err)
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if(NOT _pbdev_res EQUAL 0)
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message(STATUS "pureboot_device not built (${_pbdev_err}) — protocol tests skipped")
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unset(PB_DEVICE)
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endif()
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if(LIBAVR_MCU STREQUAL "atmega328p")
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set(TSB_DEVICE ${CMAKE_BINARY_DIR}/tsb_device)
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execute_process(
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COMMAND ${_host_cc} -O2 -I/usr/include/simavr -I/usr/include/simavr/parts
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-o ${TSB_DEVICE} ${CMAKE_CURRENT_SOURCE_DIR}/test/device.c
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-lsimavr -lsimavrparts -lelf
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RESULT_VARIABLE _dev_res ERROR_VARIABLE _dev_err)
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if(NOT _dev_res EQUAL 0)
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message(STATUS "tsb_device not built (${_dev_err}) — protocol tests skipped")
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unset(TSB_DEVICE)
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endif()
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endif()
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endif()
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endif()
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# The ELF is only a container (symbols, section headers) and is never flashed —
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# and the host tool's load_image() dispatches on extension, so handing it one
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# would silently program the header bytes. Every loader image therefore gets
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# both flashable forms beside it at link time: .hex for avrdude, and .bin for
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# the host tool's raw path (which is what the reloc and update tests convert to
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# on the fly). .eeprom is dropped — EEPROM content is its own update.
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function(add_image_outputs name)
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add_custom_command(TARGET ${name} POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -O ihex -R .eeprom
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$<TARGET_FILE:${name}> $<TARGET_FILE:${name}>.hex
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COMMAND ${CMAKE_OBJCOPY} -O binary -R .eeprom
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$<TARGET_FILE:${name}> $<TARGET_FILE:${name}>.bin)
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endfunction()
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# The TinySafeBoot protocol reimplemented on libavr in three variants that trade
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# clarity for size. Each links into the ATmega328P boot section (BOOTSZ selects
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# its size; BOOTRST vectors a reset to its base) with -nostartfiles — a polled
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# loader has no use for the crt or the vector table. The naked entry sits in
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# .vectors, laid first, and runs. The boot base is FLASHEND+1 minus the section
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# size; the linker section-start and the source's boot_bytes agree. tsb_app is
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# the application's reset vector, pinned to 0 here so the loaders jump to a
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# named function; --pmem-wrap-around lets relaxation turn that absolute jump
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# into the wrapped rjmp AVR's modulo-flash PC actually executes.
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# All three implement the full oracle feature set (see oracle/README.md):
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# watchdog bail, one-wire half-duplex, config-page activation timeout, password
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# gate, emergency erase, config/flash/EEPROM read-write. They differ only in how,
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# and the size gradient is the cost of that "how" — see dev/lessons.md.
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# tsb_asm — the tricks tier's C++ with exactly two routines in asm (the
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# bounded rx and the page-store loop — the two whose remaining
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# cost is the C ABI itself): 510 B in the 512 B section the
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# hand-written 500 B oracle occupies. Everything else, from
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# bring-up to dispatch, is C++ on libavr.
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# tsb_tricks — no asm at all: the whole-loader register allocation lives in
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# global register variables (Y walks the page pointer), every
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# helper is a tiny noinline primitive placed by the
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# global-register store rules, pages stream straight to
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# SPM/EEPROM, and the bring-up is the two reset-non-default
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# registers only. 526 B in the 1 KB section (BOOTSZ=10) — 14
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# over the oracle's section, from 168 over at this tier's first
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# floor.
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# tsb_pure — pure idiomatic libavr, one function per command, TU-local
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# (internal linkage), streaming (no SRAM page buffer): 836 B in
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# the 1 KB section.
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#
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# add_tsb_variant(<name> <boot-section-bytes>)
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function(add_tsb_variant name bytes)
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math(EXPR base_dec "32768 - ${bytes}")
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math(EXPR base_hex "${base_dec}" OUTPUT_FORMAT HEXADECIMAL)
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add_executable(${name} tsb/${name}.cpp)
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target_link_libraries(${name} PRIVATE libavr)
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target_link_options(${name} PRIVATE -nostartfiles -Wl,--section-start=.text=${base_hex}
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-Wl,--defsym=tsb_app=0 -Wl,--pmem-wrap-around=32k)
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add_custom_command(TARGET ${name} POST_BUILD COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${name}>)
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add_image_outputs(${name})
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if(PROJECT_IS_TOP_LEVEL)
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add_test(NAME ${name}.size
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COMMAND ${CMAKE_COMMAND} -DSIZE_TOOL=${CMAKE_SIZE} -DELF=$<TARGET_FILE:${name}>
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-DLIMIT=${bytes} -P ${CMAKE_CURRENT_SOURCE_DIR}/test/check_size.cmake)
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if(DEFINED TSB_DEVICE)
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add_test(NAME ${name}.protocol
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/tsbtest.py
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${TSB_DEVICE} $<TARGET_FILE:${name}> ${base_hex})
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endif()
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endif()
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endfunction()
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# The tsb tiers reimplement the ATmega328P-only reference protocol; the other
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# chips build pureboot alone.
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if(LIBAVR_MCU STREQUAL "atmega328p")
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add_tsb_variant(tsb_asm 512)
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add_tsb_variant(tsb_pure 1024)
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add_tsb_variant(tsb_tricks 1024)
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endif()
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# pureboot — the pure-constraint port (see pureboot/README.md): one source,
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# no inline assembly, no global register variables, every libavr chip,
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# fitting each chip's smallest boot sector. The geometry and the
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# pureboot_add_loader() deployment function live in pureboot/CMakeLists.txt —
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# the unit a downstream project consumes; everything below is this port's
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# own build: the stock loaders, their tests, and the size matrix. The
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# distinct binary dir keeps the `pureboot` target's output name free.
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add_subdirectory(pureboot pureboot-cmake)
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# The stock loader: the family-default deployment (crystal/RC clock, the
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# chip's natural link, default pins). The activation window stays a cache
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# variable — re-timing a deployed loader is a self-update with a re-timed
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# build. pureboot9 is that re-timed build, and what the update test installs.
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set(PUREBOOT_TIMEOUT 8 CACHE STRING "pureboot activation window, seconds")
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pureboot_add_loader(pureboot TIMEOUT ${PUREBOOT_TIMEOUT})
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if(PROJECT_IS_TOP_LEVEL)
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get_target_property(_pb_stock_hz pureboot PUREBOOT_HZ)
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get_target_property(_pb_stock_baud pureboot PUREBOOT_BAUD)
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add_test(NAME pureboot.size
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COMMAND ${CMAKE_COMMAND} -DSIZE_TOOL=${CMAKE_SIZE} -DELF=$<TARGET_FILE:pureboot>
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-DLIMIT=${PUREBOOT_LIMIT} -P ${CMAKE_CURRENT_SOURCE_DIR}/test/check_size.cmake)
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if(Python3_FOUND)
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add_test(NAME pureboot.pi
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/check_pi.py
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${CMAKE_OBJDUMP} ${CMAKE_NM} $<TARGET_FILE:pureboot> ${PUREBOOT_BASE_HEX})
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add_test(NAME pureboot.planner
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/test_planner.py
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${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py)
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endif()
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# The protocol test flashes this fixture through the loader with the real
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# host tool and expects its banner after the hand-over; a normally linked
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# application whose reset vector is what the tinies' surgery re-homes.
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if(DEFINED PB_DEVICE)
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add_executable(pbapp test/pbapp.cpp)
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target_link_libraries(pbapp PRIVATE libavr)
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add_custom_command(TARGET pbapp POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:pbapp> $<TARGET_FILE:pbapp>.bin)
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add_test(NAME pureboot.protocol
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbtest.py
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${PB_DEVICE} $<TARGET_FILE:pureboot> ${PUREBOOT_SIM_MCU} ${_pb_stock_hz}
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${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_pb_stock_baud} ${PUREBOOT_EEPROM}
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$<TARGET_FILE:pbapp>.bin ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
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${CMAKE_BINARY_DIR}/pbtest-work)
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set_tests_properties(pureboot.protocol PROPERTIES TIMEOUT 180)
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# The position-independence acceptance test: the identical image,
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# installed one slot lower, must serve the full command set.
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add_test(NAME pureboot.reloc
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbreloc.py
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${PB_DEVICE} $<TARGET_FILE:pureboot> ${PUREBOOT_SIM_MCU} ${_pb_stock_hz}
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${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_pb_stock_baud}
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${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
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${CMAKE_BINARY_DIR}/pbreloc-work)
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set_tests_properties(pureboot.reloc PROPERTIES TIMEOUT 180
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ENVIRONMENT "PB_OBJCOPY=${CMAKE_OBJCOPY}")
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# Entering the loader from a running application with no reset
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# between, over a page buffer the application dirtied — the case the
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# loader declines to guard and the host repairs. Hardware forbids the
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# state here (SPM runs only from the boot section); simavr does not,
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# which is what makes it constructible.
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if(LIBAVR_MCU STREQUAL "atmega328p")
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add_test(NAME pureboot.dirty
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbdirty.py
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${PB_DEVICE} $<TARGET_FILE:pureboot> ${PUREBOOT_SIM_MCU} ${_pb_stock_hz}
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${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_pb_stock_baud}
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$<TARGET_FILE:pbapp>.bin
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${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
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${CMAKE_BINARY_DIR}/pbdirty-work)
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set_tests_properties(pureboot.dirty PROPERTIES TIMEOUT 180)
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endif()
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# Re-homing: a loader mistakenly programmed at address 0 (a raw .bin
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# handed to a programmer) or sitting in the staging slot must heal
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# into the canonical slot through the ordinary --update-loader flow.
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# Patched-vector behavior, so one representative chip carries it.
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if(LIBAVR_MCU STREQUAL "attiny85")
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add_test(NAME pureboot.rehome
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbrehome.py
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${PB_DEVICE} $<TARGET_FILE:pureboot> $<TARGET_FILE:pureboot9>.bin
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${PUREBOOT_SIM_MCU} ${_pb_stock_hz} ${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE}
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${_pb_stock_baud} $<TARGET_FILE:pbapp>.bin
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${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
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${CMAKE_BINARY_DIR}/pbrehome-work)
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set_tests_properties(pureboot.rehome PROPERTIES TIMEOUT 180)
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endif()
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# The self-update end-to-end: the re-timed build (same source, only
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# the timeout differs — a byte-different image) replaces the resident
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# through --update-loader, with every power-fail phase rehearsed from
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# the runner's flash dumps.
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pureboot_add_loader(pureboot9 TIMEOUT 9)
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add_test(NAME pureboot.update
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbupdate.py
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${PB_DEVICE} $<TARGET_FILE:pureboot> $<TARGET_FILE:pureboot9>
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${PUREBOOT_SIM_MCU} ${_pb_stock_hz} ${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE}
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${_pb_stock_baud} $<TARGET_FILE:pbapp>.bin
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${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
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${CMAKE_BINARY_DIR}/pbupdate-work)
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set_tests_properties(pureboot.update PROPERTIES TIMEOUT 600
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ENVIRONMENT "PB_OBJCOPY=${CMAKE_OBJCOPY}")
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endif()
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# The size matrix: every configuration axis that could move the image
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# size — the serial backend (different code), the USART instance
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# (different registers), the clock (different constants), and the baud
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# through the shapes its bit timing takes — each combination must still
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# fit the chip's slot budget. Pins are size-neutral (port and bit are
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# immediate operands) and the timeout is a constant, so neither adds an
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# axis. The stock build is one point of this matrix and already has its
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# test.
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function(pureboot_size_variant name)
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pureboot_add_loader(${name} ${ARGN})
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add_test(NAME ${name}.size
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COMMAND ${CMAKE_COMMAND} -DSIZE_TOOL=${CMAKE_SIZE} -DELF=$<TARGET_FILE:${name}>
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-DLIMIT=${PUREBOOT_LIMIT} -P ${CMAKE_CURRENT_SOURCE_DIR}/test/check_size.cmake)
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endfunction()
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# The autobaud variants under review (pureboot/autobaud.md): one clock-agnostic
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# image per chip, no clock × baud axis. Both are size-tested against the same
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# per-chip budget on every chip — the decider is whether pure C++ fits 512,
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# and the 1284 is the tight one (pure 508, register 512).
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function(pureboot_autobaud_variant name source)
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pureboot_add_autobaud(${name} ${source})
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add_test(NAME ${name}.size
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COMMAND ${CMAKE_COMMAND} -DSIZE_TOOL=${CMAKE_SIZE} -DELF=$<TARGET_FILE:${name}>
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-DLIMIT=${PUREBOOT_LIMIT} -P ${CMAKE_CURRENT_SOURCE_DIR}/test/check_size.cmake)
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endfunction()
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pureboot_autobaud_variant(pureboot_autobaud_pure pureboot_autobaud_pure.cpp)
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pureboot_autobaud_variant(pureboot_autobaud_reg pureboot_autobaud_reg.cpp)
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# One point of the exhaustive matrix, named from its resolved parameters
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# so the enumeration cannot collide with itself. Unreachable rates drop
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# out here rather than aborting the configure.
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function(pureboot_matrix_point hz baud link)
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if(link STREQUAL "software")
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pureboot_baud_feasible(${hz} ${baud} 1 _ok)
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set(_args SERIAL software)
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else()
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pureboot_baud_feasible(${hz} ${baud} 0 _ok)
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set(_args USART ${link})
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endif()
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if(_ok)
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pureboot_size_variant(pbm_${hz}_${baud}_${link} CLOCK ${hz} BAUD ${baud} ${_args})
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endif()
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endfunction()
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# Clock points: the shipped-fuse floor (CKDIV8), the calibrated RC, and
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# the crystal the stock build assumes (the tiny13's ladder is its own RC
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# menu — it has no crystal option).
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if(LIBAVR_MCU MATCHES "^attiny13")
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set(_matrix_clocks 1200000 4800000 9600000)
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set(_full_clocks 128000 600000 1200000 4800000 9600000)
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else()
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set(_matrix_clocks 1000000 8000000 16000000)
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set(_full_clocks 128000 1000000 1843200 2000000 3686400 4000000 7372800 8000000
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11059200 12000000 14745600 16000000 18432000 20000000)
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endif()
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# The exhaustive cross product: every clock a deployment plausibly runs
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# — the internal oscillators, the shipped CKDIV8 floor, the plain
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# crystals and the UART crystals — against every rate, against every
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# backend. Beyond the ladder the list carries the slow rates a
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# sub-megahertz oscillator is left with, which no ladder rate reaches
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# (16000 Bd is the only rate the 128 kHz oscillator holds exactly); at
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# the fast clocks those same rates also select the software UART's
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# 16-bit _delay_loop_2 bit spin (two words more setup at each of its five
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# sites), the largest image the space produces and a shape the ladder
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# default — always the *fastest* rate a clock reaches — never picks.
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#
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# Bounded to one chip per size-bearing class: flash addressing (the
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# word-addressed 1284), hand-over shape (the patched vector on the tinies
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# and m48s), page size, and USART inventory. Everything else in the image
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# is chip-independent code, so a further chip buys builds and no
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# coverage; every chip outside the set carries the compact matrix.
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get_property(_full_bauds GLOBAL PROPERTY PUREBOOT_BAUD_LADDER)
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list(APPEND _full_bauds 16000 4800 2400 1200)
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set(_matrix_spot attiny13a attiny85 atmega48pa atmega8a atmega168pa
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atmega328p atmega164a atmega644a atmega1284p)
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if(DEFINED ENV{PUREBOOT_FULL_MATRIX} AND LIBAVR_MCU IN_LIST _matrix_spot)
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foreach(_matrix_hz IN LISTS _full_clocks)
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foreach(_matrix_baud IN LISTS _full_bauds)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} software)
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if(PUREBOOT_HAS_USART)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 0)
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endif()
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if(PUREBOOT_HAS_USART1)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 1)
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endif()
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endforeach()
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endforeach()
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else()
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foreach(_matrix_hz IN LISTS _matrix_clocks)
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math(EXPR _matrix_khz "${_matrix_hz} / 1000")
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if(PUREBOOT_HAS_USART OR NOT _matrix_hz EQUAL _pb_stock_hz)
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pureboot_size_variant(pureboot_sw_${_matrix_khz}k CLOCK ${_matrix_hz} SERIAL software)
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endif()
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if(PUREBOOT_HAS_USART AND NOT _matrix_hz EQUAL _pb_stock_hz)
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pureboot_size_variant(pureboot_hw_${_matrix_khz}k CLOCK ${_matrix_hz} SERIAL hardware)
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endif()
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if(PUREBOOT_HAS_USART1 AND NOT _matrix_hz EQUAL _pb_stock_hz)
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pureboot_size_variant(pureboot_usart1_${_matrix_khz}k CLOCK ${_matrix_hz} USART 1)
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endif()
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endforeach()
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list(GET _matrix_clocks -1 _matrix_top_hz)
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pureboot_size_variant(pureboot_sw_wide CLOCK ${_matrix_top_hz} BAUD 9600 SERIAL software)
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endif()
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if(PUREBOOT_HAS_USART1)
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pureboot_size_variant(pureboot_usart1 USART 1)
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endif()
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# One configured deployment end to end — a real board's shape rather
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# than the stock assumption: the ATmega328P on its shipped 1 MHz fuses,
|
||
# the software UART on hand-picked pins (TX = PB1, RX = PB5), the ladder
|
||
# baud (9600). The full protocol suite runs against it, fixture
|
||
# application included, over the runner's GPIO bridge — proving the
|
||
# configuration plumbing produces a working loader, not just one that
|
||
# fits.
|
||
if(LIBAVR_MCU STREQUAL "atmega328p" AND DEFINED PB_DEVICE)
|
||
pureboot_size_variant(pureboot_custom CLOCK 1000000 SERIAL software RX pb5 TX pb1)
|
||
get_target_property(_custom_hz pureboot_custom PUREBOOT_HZ)
|
||
get_target_property(_custom_baud pureboot_custom PUREBOOT_BAUD)
|
||
get_target_property(_custom_link pureboot_custom PUREBOOT_LINK)
|
||
add_executable(pbapp_custom test/pbapp.cpp)
|
||
target_link_libraries(pbapp_custom PRIVATE libavr)
|
||
target_compile_definitions(pbapp_custom PRIVATE PUREBOOT_CLOCK_HZ=${_custom_hz}
|
||
PUREBOOT_BAUD=${_custom_baud} PUREBOOT_SOFT_SERIAL PUREBOOT_TX=pb1)
|
||
add_custom_command(TARGET pbapp_custom POST_BUILD
|
||
COMMAND ${CMAKE_OBJCOPY} -O binary
|
||
$<TARGET_FILE:pbapp_custom> $<TARGET_FILE:pbapp_custom>.bin)
|
||
add_test(NAME pureboot.custom
|
||
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbtest.py
|
||
${PB_DEVICE} $<TARGET_FILE:pureboot_custom> ${PUREBOOT_SIM_MCU} ${_custom_hz}
|
||
${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_custom_baud} ${PUREBOOT_EEPROM}
|
||
$<TARGET_FILE:pbapp_custom>.bin ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
|
||
${CMAKE_BINARY_DIR}/pbcustom-work ${_custom_link})
|
||
set_tests_properties(pureboot.custom PROPERTIES TIMEOUT 180)
|
||
endif()
|
||
|
||
# The second USART, driven for real on one chip: instance selection is
|
||
# compile-checked everywhere, but only a live session proves the loader
|
||
# initialized and polls the USART it claims to. The fixture application
|
||
# banners on the same instance.
|
||
if(LIBAVR_MCU STREQUAL "atmega644a" AND DEFINED PB_DEVICE)
|
||
get_target_property(_usart1_hz pureboot_usart1 PUREBOOT_HZ)
|
||
get_target_property(_usart1_baud pureboot_usart1 PUREBOOT_BAUD)
|
||
add_executable(pbapp_usart1 test/pbapp.cpp)
|
||
target_link_libraries(pbapp_usart1 PRIVATE libavr)
|
||
target_compile_definitions(pbapp_usart1 PRIVATE PUREBOOT_CLOCK_HZ=${_usart1_hz}
|
||
PUREBOOT_BAUD=${_usart1_baud} PUREBOOT_USART=1)
|
||
add_custom_command(TARGET pbapp_usart1 POST_BUILD
|
||
COMMAND ${CMAKE_OBJCOPY} -O binary
|
||
$<TARGET_FILE:pbapp_usart1> $<TARGET_FILE:pbapp_usart1>.bin)
|
||
add_test(NAME pureboot.usart1
|
||
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbtest.py
|
||
${PB_DEVICE} $<TARGET_FILE:pureboot_usart1> ${PUREBOOT_SIM_MCU} ${_usart1_hz}
|
||
${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_usart1_baud} ${PUREBOOT_EEPROM}
|
||
$<TARGET_FILE:pbapp_usart1>.bin ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
|
||
${CMAKE_BINARY_DIR}/pbusart1-work usart1)
|
||
set_tests_properties(pureboot.usart1 PROPERTIES TIMEOUT 180)
|
||
endif()
|
||
|
||
# The autobaud variants driven end to end over the software-UART bridge (both
|
||
# under review — pureboot/autobaud.md): the host sends the 0xC0 calibration
|
||
# pulse, the loader times it, locks, and programs. Run on the near-flash 328P
|
||
# and the word-addressed 1284P — the two flash-addressing classes — and each
|
||
# at two clocks with the one binary, which is the clock-agnostic property
|
||
# autobaud exists for (test/pbautobaud.py). The fixture application banners
|
||
# over the same software link at the first clock's rate.
|
||
if(LIBAVR_MCU MATCHES "^atmega(328p|1284p)$" AND DEFINED PB_DEVICE)
|
||
add_executable(pbapp_autobaud test/pbapp.cpp)
|
||
target_link_libraries(pbapp_autobaud PRIVATE libavr)
|
||
target_compile_definitions(pbapp_autobaud PRIVATE PUREBOOT_CLOCK_HZ=1000000
|
||
PUREBOOT_BAUD=9600 PUREBOOT_SOFT_SERIAL PUREBOOT_TX=pb1)
|
||
add_custom_command(TARGET pbapp_autobaud POST_BUILD
|
||
COMMAND ${CMAKE_OBJCOPY} -O binary
|
||
$<TARGET_FILE:pbapp_autobaud> $<TARGET_FILE:pbapp_autobaud>.bin)
|
||
foreach(_variant pure reg)
|
||
add_test(NAME pureboot.autobaud_${_variant}
|
||
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbautobaud.py
|
||
${PB_DEVICE} $<TARGET_FILE:pureboot_autobaud_${_variant}> ${PUREBOOT_SIM_MCU}
|
||
${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} $<TARGET_FILE:pbapp_autobaud>.bin
|
||
1000000 9600 ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
|
||
${CMAKE_BINARY_DIR}/pbautobaud-${_variant}-work)
|
||
set_tests_properties(pureboot.autobaud_${_variant} PROPERTIES TIMEOUT 240)
|
||
endforeach()
|
||
endif()
|
||
endif()
|