BlackMark 0f00f6bdeb test: move the handshake regression in beside the rest ...

It was written next to the loader source; the harness lives at the repo root.
Not registered with ctest yet — it belongs beside pureboot.planner, which is
the other test of the host tool's pure logic.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-07-24 18:22:19 +02:00

..

check_pi.py

pureboot 5: one command pair for every memory, and a clock-free backend

2026-07-24 15:50:48 +02:00

check_size.cmake

tsb: reimplement TinySafeBoot on libavr in three size tiers

2026-07-19 05:00:51 +02:00

device.c

tsb: asm tier reaches full oracle feature parity at 502 B

2026-07-19 16:23:16 +02:00

pbapp.cpp

pureboot 3: a 512-byte slot on every chip, the 1284s included

2026-07-22 20:49:23 +02:00

pbautobaud.py

pureboot: the unified autobaud loader, and the hang that settled the decision

2026-07-24 00:48:54 +02:00

pbdirty.py

pureboot 3: a 512-byte slot on every chip, the 1284s included

2026-07-22 20:49:23 +02:00

pbrehome.py

pureboot 3: a 512-byte slot on every chip, the 1284s included

2026-07-22 20:49:23 +02:00

pbreloc.py

pureboot 3: a 512-byte slot on every chip, the 1284s included

2026-07-22 20:49:23 +02:00

pbsim.py

pureboot: every deployment axis is a build parameter

2026-07-21 23:42:57 +02:00

pbtest.py

pureboot 5: one command pair for every memory, and a clock-free backend

2026-07-24 15:50:48 +02:00

pbupdate.py

pureboot 3: a 512-byte slot on every chip, the 1284s included

2026-07-22 20:49:23 +02:00

pureboot_device.c

pureboot 5: one command pair for every memory, and a clock-free backend

2026-07-24 15:50:48 +02:00

test_handshake.py

test: move the handshake regression in beside the rest

2026-07-24 18:22:19 +02:00

test_planner.py

pureboot 5: one command pair for every memory, and a clock-free backend

2026-07-24 15:50:48 +02:00

tsbtest.py

tsb: protocol test covers the password gate and emergency erase

2026-07-19 16:49:20 +02:00