pureboot: the info block is what proves a knock landed

A prompt byte alone does not: one left over from a previous session can
still be in the pipeline while the port opening resets the device into a
fresh window, where the bare command that follows is discarded. Each
attempt is now the whole handshake, retried until the block comes back.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "libavr"]
+	path = libavr
+	url = ../libavr.git

CMakeLists.txt

@@ -8,6 +8,9 @@ include(FetchContent)
 if(NOT LIBAVR_ROOT AND DEFINED ENV{LIBAVR_ROOT})
 	set(LIBAVR_ROOT $ENV{LIBAVR_ROOT})
 endif()
+if(NOT LIBAVR_ROOT)
+	set(LIBAVR_ROOT ${CMAKE_CURRENT_SOURCE_DIR}/libavr)
+endif()
 if(LIBAVR_ROOT)
 	FetchContent_Declare(libavr SOURCE_DIR ${LIBAVR_ROOT})
 else()
@@ -126,154 +129,31 @@ if(LIBAVR_MCU STREQUAL "atmega328p")
 endif()
 
 # pureboot — the pure-constraint port (see pureboot/README.md): one source,
-# no inline assembly, no global register variables, every libavr chip, 512
-# bytes each. The loader owns the top 512 bytes of flash on every chip; the
-# application entry symbol is address 0 on the mega (reset re-vectors to the
-# loader through BOOTRST, so word 0 stays the application's own vector) and
-# the trampoline word just below the loader on the tinies (host-side vector
-# surgery points it at the application). --pmem-wrap-around models AVR's
-# modulo-flash PC where the flash is big enough to need it.
-#
-# The image is position-independent (check_pi.py asserts the two link-time
-# facts that make it so), and on the tinies its budget is 510, not 512: the
-# slot's last word is the trampoline the host composes — the resident slot's
-# holds the application entry, and a staging copy's holds the jump through
-# which it reaches the loader it installed. The activation window is a
-# compile-time constant; a different PUREBOOT_TIMEOUT builds the re-timed
-# binary a self-update then installs.
+# no inline assembly, no global register variables, every libavr chip,
+# fitting each chip's smallest boot sector. The geometry and the
+# pureboot_add_loader() deployment function live in pureboot/CMakeLists.txt —
+# the unit a downstream project consumes; everything below is this port's
+# own build: the stock loaders, their tests, and the size matrix. The
+# distinct binary dir keeps the `pureboot` target's output name free.
+add_subdirectory(pureboot pureboot-cmake)
+
+# The stock loader: the family-default deployment (crystal/RC clock, the
+# chip's natural link, default pins). The activation window stays a cache
+# variable — re-timing a deployed loader is a self-update with a re-timed
+# build. pureboot9 is that re-timed build, and what the update test installs.
 set(PUREBOOT_TIMEOUT 8 CACHE STRING "pureboot activation window, seconds")
-# Per-family geometry. The boot-sectioned megas run the loader from the
-# hardware boot section and boot the application at word 0; the tinies and
-# the boot-section-less m48s get the trampoline surgery. All megas assume a
-# 16 MHz crystal at 115200 Bd; the tinies their internal RC at 57600 Bd over
-# the software UART. --pmem-wrap-around models AVR's modulo-flash PC where
-# the flash is big enough to need it (an rjmp reaches all of 4 KiB by
-# itself).
-if(LIBAVR_MCU MATCHES "^attiny13a?$")
-	set(_pb_flash 1024)
-	set(_pb_wrap "")
-	set(_pb_page 32)
-	set(_pb_hz 9600000)
-	set(_pb_baud 57600)
-	set(_pb_eeprom 64)
-elseif(LIBAVR_MCU STREQUAL "attiny25")
-	set(_pb_flash 2048)
-	set(_pb_wrap "")
-	set(_pb_page 32)
-	set(_pb_hz 8000000)
-	set(_pb_baud 57600)
-	set(_pb_eeprom 128)
-elseif(LIBAVR_MCU STREQUAL "attiny45")
-	set(_pb_flash 4096)
-	set(_pb_wrap "")
-	set(_pb_page 64)
-	set(_pb_hz 8000000)
-	set(_pb_baud 57600)
-	set(_pb_eeprom 256)
-elseif(LIBAVR_MCU STREQUAL "attiny85")
-	set(_pb_flash 8192)
-	set(_pb_wrap -Wl,--pmem-wrap-around=8k)
-	set(_pb_page 64)
-	set(_pb_hz 8000000)
-	set(_pb_baud 57600)
-	set(_pb_eeprom 512)
-elseif(LIBAVR_MCU MATCHES "^atmega48(a|p|pa)?$")
-	set(_pb_flash 4096)
-	set(_pb_wrap "")
-	set(_pb_page 64)
-	set(_pb_hz 16000000)
-	set(_pb_baud 115200)
-	set(_pb_eeprom 256)
-elseif(LIBAVR_MCU MATCHES "^atmega8a?$" OR LIBAVR_MCU MATCHES "^atmega88(a|p|pa)?$")
-	set(_pb_flash 8192)
-	set(_pb_wrap -Wl,--pmem-wrap-around=8k)
-	set(_pb_page 64)
-	set(_pb_hz 16000000)
-	set(_pb_baud 115200)
-	set(_pb_eeprom 512)
-elseif(LIBAVR_MCU MATCHES "^atmega16a?$" OR LIBAVR_MCU MATCHES "^atmega168(a|p|pa)?$" OR
-       LIBAVR_MCU MATCHES "^atmega164(a|p|pa)$")
-	set(_pb_flash 16384)
-	set(_pb_wrap -Wl,--pmem-wrap-around=16k)
-	set(_pb_page 128)
-	set(_pb_hz 16000000)
-	set(_pb_baud 115200)
-	set(_pb_eeprom 512)
-elseif(LIBAVR_MCU MATCHES "^atmega32a?$" OR LIBAVR_MCU MATCHES "^atmega328p?$" OR
-       LIBAVR_MCU MATCHES "^atmega324(a|p|pa)$")
-	set(_pb_flash 32768)
-	set(_pb_wrap -Wl,--pmem-wrap-around=32k)
-	set(_pb_page 128)
-	set(_pb_hz 16000000)
-	set(_pb_baud 115200)
-	set(_pb_eeprom 1024)
-elseif(LIBAVR_MCU MATCHES "^atmega644(a|p|pa)?$")
-	# 64 KiB is exactly the 16-bit byte space: plain LPM reaches everything,
-	# and the smallest boot section (1 KiB) holds the loader and its staging
-	# slot together (see pureboot/README.md).
-	set(_pb_flash 65536)
-	set(_pb_wrap -Wl,--pmem-wrap-around=64k)
-	set(_pb_page 256)
-	set(_pb_hz 16000000)
-	set(_pb_baud 115200)
-	set(_pb_eeprom 2048)
-elseif(LIBAVR_MCU MATCHES "^atmega1284p?$")
-	# 128 KiB: wire flash addresses are word addresses, reads go through
-	# ELPM, and the PC's modulo wrap exceeds what --pmem-wrap-around models.
-	# The slot is 1 KiB — this chip's own smallest boot sector; the far
-	# machinery cannot fit 512 B (see pureboot/README.md).
-	set(_pb_flash 131072)
-	set(_pb_wrap "")
-	set(_pb_page 256)
-	set(_pb_hz 16000000)
-	set(_pb_baud 115200)
-	set(_pb_eeprom 4096)
-	set(_pb_slot 1024)
-	set(_pb_limit 1024)
-else()
-	message(FATAL_ERROR "pureboot: no geometry for ${LIBAVR_MCU}")
-endif()
-if(NOT DEFINED _pb_slot)
-	set(_pb_slot 512)
-endif()
-math(EXPR _pb_base "${_pb_flash} - ${_pb_slot}")
-math(EXPR _pb_base_hex "${_pb_base}" OUTPUT_FORMAT HEXADECIMAL)
-# Patched-vector chips hand over through the trampoline word below the slot,
-# which is also the slot's own last word — their budget is slot − 2.
-if(LIBAVR_MCU MATCHES "^atmega" AND NOT LIBAVR_MCU MATCHES "^atmega48")
-	set(_pb_app 0)
-	if(NOT DEFINED _pb_limit)
-		set(_pb_limit ${_pb_slot})
-	endif()
-else()
-	math(EXPR _pb_app "${_pb_base} - 2")
-	math(EXPR _pb_limit "${_pb_slot} - 2")
-endif()
-
-# simavr names its cores after the base dies; the A revisions run on them
-# (the 644PA on the 644P core).
-set(_pb_sim_mcu ${LIBAVR_MCU})
-if(LIBAVR_MCU MATCHES "^atmega(8|16|32|48|88|164|168|644)a$")
-	string(REGEX REPLACE "a$" "" _pb_sim_mcu ${LIBAVR_MCU})
-elseif(LIBAVR_MCU STREQUAL "atmega644pa")
-	set(_pb_sim_mcu atmega644p)
-endif()
-
-add_executable(pureboot pureboot/pureboot.cpp)
-target_link_libraries(pureboot PRIVATE libavr)
-target_compile_definitions(pureboot PRIVATE PUREBOOT_TIMEOUT=${PUREBOOT_TIMEOUT})
-target_link_options(pureboot PRIVATE -nostartfiles -Wl,--section-start=.text=${_pb_base_hex}
-                    -Wl,--defsym=pureboot_app=${_pb_app} ${_pb_wrap})
-add_custom_command(TARGET pureboot POST_BUILD COMMAND ${CMAKE_SIZE} $<TARGET_FILE:pureboot>)
-add_image_outputs(pureboot)
+pureboot_add_loader(pureboot TIMEOUT ${PUREBOOT_TIMEOUT})
 if(PROJECT_IS_TOP_LEVEL)
+	get_target_property(_pb_stock_hz pureboot PUREBOOT_HZ)
+	get_target_property(_pb_stock_baud pureboot PUREBOOT_BAUD)
+
 	add_test(NAME pureboot.size
 	         COMMAND ${CMAKE_COMMAND} -DSIZE_TOOL=${CMAKE_SIZE} -DELF=$<TARGET_FILE:pureboot>
-	                 -DLIMIT=${_pb_limit} -P ${CMAKE_CURRENT_SOURCE_DIR}/test/check_size.cmake)
+	                 -DLIMIT=${PUREBOOT_LIMIT} -P ${CMAKE_CURRENT_SOURCE_DIR}/test/check_size.cmake)
 	if(Python3_FOUND)
 		add_test(NAME pureboot.pi
 		         COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/check_pi.py
-		                 ${CMAKE_OBJDUMP} ${CMAKE_NM} $<TARGET_FILE:pureboot> ${_pb_base_hex})
+		                 ${CMAKE_OBJDUMP} ${CMAKE_NM} $<TARGET_FILE:pureboot> ${PUREBOOT_BASE_HEX})
 		add_test(NAME pureboot.planner
 		         COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/test_planner.py
 		                 ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py)
@@ -289,9 +169,9 @@ if(PROJECT_IS_TOP_LEVEL)
 		                   COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:pbapp> $<TARGET_FILE:pbapp>.bin)
 		add_test(NAME pureboot.protocol
 		         COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbtest.py
-		                 ${PB_DEVICE} $<TARGET_FILE:pureboot> ${_pb_sim_mcu} ${_pb_hz} ${_pb_base_hex}
-		                 ${_pb_page} ${_pb_baud} ${_pb_eeprom} $<TARGET_FILE:pbapp>.bin
-		                 ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
+		                 ${PB_DEVICE} $<TARGET_FILE:pureboot> ${PUREBOOT_SIM_MCU} ${_pb_stock_hz}
+		                 ${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_pb_stock_baud} ${PUREBOOT_EEPROM}
+		                 $<TARGET_FILE:pbapp>.bin ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
 		                 ${CMAKE_BINARY_DIR}/pbtest-work)
 		set_tests_properties(pureboot.protocol PROPERTIES TIMEOUT 180)
 
@@ -299,43 +179,203 @@ if(PROJECT_IS_TOP_LEVEL)
 		# installed one slot lower, must serve the full command set.
 		add_test(NAME pureboot.reloc
 		         COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbreloc.py
-		                 ${PB_DEVICE} $<TARGET_FILE:pureboot> ${_pb_sim_mcu} ${_pb_hz} ${_pb_base_hex}
-		                 ${_pb_page} ${_pb_baud} ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
+		                 ${PB_DEVICE} $<TARGET_FILE:pureboot> ${PUREBOOT_SIM_MCU} ${_pb_stock_hz}
+		                 ${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_pb_stock_baud}
+		                 ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
 		                 ${CMAKE_BINARY_DIR}/pbreloc-work)
 		set_tests_properties(pureboot.reloc PROPERTIES TIMEOUT 180
 		                     ENVIRONMENT "PB_OBJCOPY=${CMAKE_OBJCOPY}")
 
+		# Entering the loader from a running application with no reset
+		# between, over a page buffer the application dirtied — the case the
+		# loader declines to guard and the host repairs. Hardware forbids the
+		# state here (SPM runs only from the boot section); simavr does not,
+		# which is what makes it constructible.
+		if(LIBAVR_MCU STREQUAL "atmega328p")
+			add_test(NAME pureboot.dirty
+			         COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbdirty.py
+			                 ${PB_DEVICE} $<TARGET_FILE:pureboot> ${PUREBOOT_SIM_MCU} ${_pb_stock_hz}
+			                 ${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_pb_stock_baud}
+			                 $<TARGET_FILE:pbapp>.bin
+			                 ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
+			                 ${CMAKE_BINARY_DIR}/pbdirty-work)
+			set_tests_properties(pureboot.dirty PROPERTIES TIMEOUT 180)
+		endif()
+
 		# Re-homing: a loader mistakenly programmed at address 0 (a raw .bin
-		# handed to a programmer) must heal into the canonical slot through
-		# the ordinary --update-loader flow. Patched-vector behavior, so one
-		# representative chip carries it.
+		# handed to a programmer) or sitting in the staging slot must heal
+		# into the canonical slot through the ordinary --update-loader flow.
+		# Patched-vector behavior, so one representative chip carries it.
 		if(LIBAVR_MCU STREQUAL "attiny85")
 			add_test(NAME pureboot.rehome
 			         COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbrehome.py
-			                 ${PB_DEVICE} $<TARGET_FILE:pureboot> $<TARGET_FILE:pureboot9>.bin ${_pb_sim_mcu}
-			                 ${_pb_hz} ${_pb_base_hex} ${_pb_page} ${_pb_baud} $<TARGET_FILE:pbapp>.bin
+			                 ${PB_DEVICE} $<TARGET_FILE:pureboot> $<TARGET_FILE:pureboot9>.bin
+			                 ${PUREBOOT_SIM_MCU} ${_pb_stock_hz} ${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE}
+			                 ${_pb_stock_baud} $<TARGET_FILE:pbapp>.bin
 			                 ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
 			                 ${CMAKE_BINARY_DIR}/pbrehome-work)
 			set_tests_properties(pureboot.rehome PROPERTIES TIMEOUT 180)
 		endif()
 
 		# The self-update end-to-end: the re-timed build (same source, only
-		# PUREBOOT_TIMEOUT differs — a byte-different image) replaces the
-		# resident through --update-loader, with every power-fail phase
-		# rehearsed from the runner's flash dumps.
-		add_executable(pureboot9 pureboot/pureboot.cpp)
-		target_link_libraries(pureboot9 PRIVATE libavr)
-		target_compile_definitions(pureboot9 PRIVATE PUREBOOT_TIMEOUT=9)
-		target_link_options(pureboot9 PRIVATE -nostartfiles -Wl,--section-start=.text=${_pb_base_hex}
-		                    -Wl,--defsym=pureboot_app=${_pb_app} ${_pb_wrap})
-		add_image_outputs(pureboot9)
+		# the timeout differs — a byte-different image) replaces the resident
+		# through --update-loader, with every power-fail phase rehearsed from
+		# the runner's flash dumps.
+		pureboot_add_loader(pureboot9 TIMEOUT 9)
 		add_test(NAME pureboot.update
 		         COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbupdate.py
-		                 ${PB_DEVICE} $<TARGET_FILE:pureboot> $<TARGET_FILE:pureboot9> ${_pb_sim_mcu}
-		                 ${_pb_hz} ${_pb_base_hex} ${_pb_page} ${_pb_baud} $<TARGET_FILE:pbapp>.bin
+		                 ${PB_DEVICE} $<TARGET_FILE:pureboot> $<TARGET_FILE:pureboot9>
+		                 ${PUREBOOT_SIM_MCU} ${_pb_stock_hz} ${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE}
+		                 ${_pb_stock_baud} $<TARGET_FILE:pbapp>.bin
 		                 ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
 		                 ${CMAKE_BINARY_DIR}/pbupdate-work)
 		set_tests_properties(pureboot.update PROPERTIES TIMEOUT 600
 		                     ENVIRONMENT "PB_OBJCOPY=${CMAKE_OBJCOPY}")
 	endif()
+
+	# The size matrix: every configuration axis that could move the image
+	# size — the serial backend (different code), the USART instance
+	# (different registers), the clock (different constants), and the baud
+	# through the shapes its bit timing takes — each combination must still
+	# fit the chip's slot budget. Pins are size-neutral (port and bit are
+	# immediate operands) and the timeout is a constant, so neither adds an
+	# axis. The stock build is one point of this matrix and already has its
+	# test.
+	function(pureboot_size_variant name)
+		pureboot_add_loader(${name} ${ARGN})
+		add_test(NAME ${name}.size
+		         COMMAND ${CMAKE_COMMAND} -DSIZE_TOOL=${CMAKE_SIZE} -DELF=$<TARGET_FILE:${name}>
+		                 -DLIMIT=${PUREBOOT_LIMIT} -P ${CMAKE_CURRENT_SOURCE_DIR}/test/check_size.cmake)
+	endfunction()
+
+	# One point of the exhaustive matrix, named from its resolved parameters
+	# so the enumeration cannot collide with itself. Unreachable rates drop
+	# out here rather than aborting the configure.
+	function(pureboot_matrix_point hz baud link)
+		if(link STREQUAL "software")
+			pureboot_baud_feasible(${hz} ${baud} 1 _ok)
+			set(_args SERIAL software)
+		else()
+			pureboot_baud_feasible(${hz} ${baud} 0 _ok)
+			set(_args USART ${link})
+		endif()
+		if(_ok)
+			pureboot_size_variant(pbm_${hz}_${baud}_${link} CLOCK ${hz} BAUD ${baud} ${_args})
+		endif()
+	endfunction()
+
+	# Clock points: the shipped-fuse floor (CKDIV8), the calibrated RC, and
+	# the crystal the stock build assumes (the tiny13's ladder is its own RC
+	# menu — it has no crystal option).
+	if(LIBAVR_MCU MATCHES "^attiny13")
+		set(_matrix_clocks 1200000 4800000 9600000)
+		set(_full_clocks 128000 600000 1200000 4800000 9600000)
+	else()
+		set(_matrix_clocks 1000000 8000000 16000000)
+		set(_full_clocks 128000 1000000 1843200 2000000 3686400 4000000 7372800 8000000
+		                 11059200 12000000 14745600 16000000 18432000 20000000)
+	endif()
+
+	# The exhaustive cross product: every clock a deployment plausibly runs
+	# — the internal oscillators, the shipped CKDIV8 floor, the plain
+	# crystals and the UART crystals — against every rate, against every
+	# backend. Beyond the ladder the list carries the slow rates a
+	# sub-megahertz oscillator is left with, which no ladder rate reaches
+	# (16000 Bd is the only rate the 128 kHz oscillator holds exactly); at
+	# the fast clocks those same rates also select the software UART's
+	# 16-bit _delay_loop_2 bit spin (two words more setup at each of its five
+	# sites), the largest image the space produces and a shape the ladder
+	# default — always the *fastest* rate a clock reaches — never picks.
+	#
+	# Bounded to one chip per size-bearing class: flash addressing (the
+	# word-addressed 1284), hand-over shape (the patched vector on the tinies
+	# and m48s), page size, and USART inventory. Everything else in the image
+	# is chip-independent code, so a further chip buys builds and no
+	# coverage; every chip outside the set carries the compact matrix.
+	get_property(_full_bauds GLOBAL PROPERTY PUREBOOT_BAUD_LADDER)
+	list(APPEND _full_bauds 16000 4800 2400 1200)
+	set(_matrix_spot attiny13a attiny85 atmega48pa atmega8a atmega168pa
+	                 atmega328p atmega164a atmega644a atmega1284p)
+	if(DEFINED ENV{PUREBOOT_FULL_MATRIX} AND LIBAVR_MCU IN_LIST _matrix_spot)
+		foreach(_matrix_hz IN LISTS _full_clocks)
+			foreach(_matrix_baud IN LISTS _full_bauds)
+				pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} software)
+				if(PUREBOOT_HAS_USART)
+					pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 0)
+				endif()
+				if(PUREBOOT_HAS_USART1)
+					pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 1)
+				endif()
+			endforeach()
+		endforeach()
+	else()
+		foreach(_matrix_hz IN LISTS _matrix_clocks)
+			math(EXPR _matrix_khz "${_matrix_hz} / 1000")
+			if(PUREBOOT_HAS_USART OR NOT _matrix_hz EQUAL _pb_stock_hz)
+				pureboot_size_variant(pureboot_sw_${_matrix_khz}k CLOCK ${_matrix_hz} SERIAL software)
+			endif()
+			if(PUREBOOT_HAS_USART AND NOT _matrix_hz EQUAL _pb_stock_hz)
+				pureboot_size_variant(pureboot_hw_${_matrix_khz}k CLOCK ${_matrix_hz} SERIAL hardware)
+			endif()
+			if(PUREBOOT_HAS_USART1 AND NOT _matrix_hz EQUAL _pb_stock_hz)
+				pureboot_size_variant(pureboot_usart1_${_matrix_khz}k CLOCK ${_matrix_hz} USART 1)
+			endif()
+		endforeach()
+		list(GET _matrix_clocks -1 _matrix_top_hz)
+		pureboot_size_variant(pureboot_sw_wide CLOCK ${_matrix_top_hz} BAUD 9600 SERIAL software)
+	endif()
+	if(PUREBOOT_HAS_USART1)
+		pureboot_size_variant(pureboot_usart1 USART 1)
+	endif()
+
+	# One configured deployment end to end — a real board's shape rather
+	# than the stock assumption: the ATmega328P on its shipped 1 MHz fuses,
+	# the software UART on hand-picked pins (TX = PB1, RX = PB5), the ladder
+	# baud (9600). The full protocol suite runs against it, fixture
+	# application included, over the runner's GPIO bridge — proving the
+	# configuration plumbing produces a working loader, not just one that
+	# fits.
+	if(LIBAVR_MCU STREQUAL "atmega328p" AND DEFINED PB_DEVICE)
+		pureboot_size_variant(pureboot_custom CLOCK 1000000 SERIAL software RX pb5 TX pb1)
+		get_target_property(_custom_hz pureboot_custom PUREBOOT_HZ)
+		get_target_property(_custom_baud pureboot_custom PUREBOOT_BAUD)
+		get_target_property(_custom_link pureboot_custom PUREBOOT_LINK)
+		add_executable(pbapp_custom test/pbapp.cpp)
+		target_link_libraries(pbapp_custom PRIVATE libavr)
+		target_compile_definitions(pbapp_custom PRIVATE PUREBOOT_CLOCK_HZ=${_custom_hz}
+		                           PUREBOOT_BAUD=${_custom_baud} PUREBOOT_SOFT_SERIAL PUREBOOT_TX=pb1)
+		add_custom_command(TARGET pbapp_custom POST_BUILD
+		                   COMMAND ${CMAKE_OBJCOPY} -O binary
+		                           $<TARGET_FILE:pbapp_custom> $<TARGET_FILE:pbapp_custom>.bin)
+		add_test(NAME pureboot.custom
+		         COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbtest.py
+		                 ${PB_DEVICE} $<TARGET_FILE:pureboot_custom> ${PUREBOOT_SIM_MCU} ${_custom_hz}
+		                 ${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_custom_baud} ${PUREBOOT_EEPROM}
+		                 $<TARGET_FILE:pbapp_custom>.bin ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
+		                 ${CMAKE_BINARY_DIR}/pbcustom-work ${_custom_link})
+		set_tests_properties(pureboot.custom PROPERTIES TIMEOUT 180)
+	endif()
+
+	# The second USART, driven for real on one chip: instance selection is
+	# compile-checked everywhere, but only a live session proves the loader
+	# initialized and polls the USART it claims to. The fixture application
+	# banners on the same instance.
+	if(LIBAVR_MCU STREQUAL "atmega644a" AND DEFINED PB_DEVICE)
+		get_target_property(_usart1_hz pureboot_usart1 PUREBOOT_HZ)
+		get_target_property(_usart1_baud pureboot_usart1 PUREBOOT_BAUD)
+		add_executable(pbapp_usart1 test/pbapp.cpp)
+		target_link_libraries(pbapp_usart1 PRIVATE libavr)
+		target_compile_definitions(pbapp_usart1 PRIVATE PUREBOOT_CLOCK_HZ=${_usart1_hz}
+		                           PUREBOOT_BAUD=${_usart1_baud} PUREBOOT_USART=1)
+		add_custom_command(TARGET pbapp_usart1 POST_BUILD
+		                   COMMAND ${CMAKE_OBJCOPY} -O binary
+		                           $<TARGET_FILE:pbapp_usart1> $<TARGET_FILE:pbapp_usart1>.bin)
+		add_test(NAME pureboot.usart1
+		         COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbtest.py
+		                 ${PB_DEVICE} $<TARGET_FILE:pureboot_usart1> ${PUREBOOT_SIM_MCU} ${_usart1_hz}
+		                 ${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_usart1_baud} ${PUREBOOT_EEPROM}
+		                 $<TARGET_FILE:pbapp_usart1>.bin ${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
+		                 ${CMAKE_BINARY_DIR}/pbusart1-work usart1)
+		set_tests_properties(pureboot.usart1 PROPERTIES TIMEOUT 180)
+	endif()
 endif()

pureboot/CMakeLists.txt

@@ -0,0 +1,312 @@
+# pureboot as a consumable CMake unit: the per-chip geometry, the default baud
+# ladder, and pureboot_add_loader() — the one way a loader target is created.
+# A downstream project brings its usual libavr setup (the `libavr` target and
+# the LIBAVR_MCU toolchain preset), adds this directory, and states its
+# deployment; every argument is optional (README.md):
+#
+#   add_subdirectory(bootloader/pureboot)
+#   pureboot_add_loader(myboot CLOCK 1000000 SERIAL software TX pb1 RX pb5)
+
+# Per-family geometry, deployment defaults, and the linker wrap the PC modulo
+# needs. The slot is 512 bytes on every chip. The USART flags mirror the
+# hardware inventory the loader's own static asserts check — the plain 644 is
+# the x4 family's one single-USART die (Atmel-2593).
+set(_pb_has_usart 1)
+set(_pb_has_usart1 0)
+if(LIBAVR_MCU MATCHES "^attiny13a?$")
+	set(_pb_flash 1024)
+	set(_pb_wrap "")
+	set(_pb_page 32)
+	set(_pb_hz 9600000)
+	set(_pb_eeprom 64)
+	set(_pb_has_usart 0)
+elseif(LIBAVR_MCU STREQUAL "attiny25")
+	set(_pb_flash 2048)
+	set(_pb_wrap "")
+	set(_pb_page 32)
+	set(_pb_hz 8000000)
+	set(_pb_eeprom 128)
+	set(_pb_has_usart 0)
+elseif(LIBAVR_MCU STREQUAL "attiny45")
+	set(_pb_flash 4096)
+	set(_pb_wrap "")
+	set(_pb_page 64)
+	set(_pb_hz 8000000)
+	set(_pb_eeprom 256)
+	set(_pb_has_usart 0)
+elseif(LIBAVR_MCU STREQUAL "attiny85")
+	set(_pb_flash 8192)
+	set(_pb_wrap -Wl,--pmem-wrap-around=8k)
+	set(_pb_page 64)
+	set(_pb_hz 8000000)
+	set(_pb_eeprom 512)
+	set(_pb_has_usart 0)
+elseif(LIBAVR_MCU MATCHES "^atmega48(a|p|pa)?$")
+	set(_pb_flash 4096)
+	set(_pb_wrap "")
+	set(_pb_page 64)
+	set(_pb_hz 16000000)
+	set(_pb_eeprom 256)
+elseif(LIBAVR_MCU MATCHES "^atmega8a?$" OR LIBAVR_MCU MATCHES "^atmega88(a|p|pa)?$")
+	set(_pb_flash 8192)
+	set(_pb_wrap -Wl,--pmem-wrap-around=8k)
+	set(_pb_page 64)
+	set(_pb_hz 16000000)
+	set(_pb_eeprom 512)
+elseif(LIBAVR_MCU MATCHES "^atmega16a?$" OR LIBAVR_MCU MATCHES "^atmega168(a|p|pa)?$")
+	set(_pb_flash 16384)
+	set(_pb_wrap -Wl,--pmem-wrap-around=16k)
+	set(_pb_page 128)
+	set(_pb_hz 16000000)
+	set(_pb_eeprom 512)
+elseif(LIBAVR_MCU MATCHES "^atmega164(a|p|pa)$")
+	set(_pb_flash 16384)
+	set(_pb_wrap -Wl,--pmem-wrap-around=16k)
+	set(_pb_page 128)
+	set(_pb_hz 16000000)
+	set(_pb_eeprom 512)
+	set(_pb_has_usart1 1)
+elseif(LIBAVR_MCU MATCHES "^atmega32a?$" OR LIBAVR_MCU MATCHES "^atmega328p?$")
+	set(_pb_flash 32768)
+	set(_pb_wrap -Wl,--pmem-wrap-around=32k)
+	set(_pb_page 128)
+	set(_pb_hz 16000000)
+	set(_pb_eeprom 1024)
+elseif(LIBAVR_MCU MATCHES "^atmega324(a|p|pa)$")
+	set(_pb_flash 32768)
+	set(_pb_wrap -Wl,--pmem-wrap-around=32k)
+	set(_pb_page 128)
+	set(_pb_hz 16000000)
+	set(_pb_eeprom 1024)
+	set(_pb_has_usart1 1)
+elseif(LIBAVR_MCU MATCHES "^atmega644(a|p|pa)?$")
+	# 64 KiB is exactly the 16-bit byte space, so plain LPM still reaches
+	# everything and the wire stays byte-addressed. The plain 644 is the
+	# family's one single-USART die.
+	set(_pb_flash 65536)
+	set(_pb_wrap -Wl,--pmem-wrap-around=64k)
+	set(_pb_page 256)
+	set(_pb_hz 16000000)
+	set(_pb_eeprom 2048)
+	if(NOT LIBAVR_MCU STREQUAL "atmega644")
+		set(_pb_has_usart1 1)
+	endif()
+elseif(LIBAVR_MCU MATCHES "^atmega1284p?$")
+	# 128 KiB: wire addresses are words, reads go through ELPM, and the PC's
+	# modulo wrap exceeds what --pmem-wrap-around models.
+	set(_pb_flash 131072)
+	set(_pb_wrap "")
+	set(_pb_page 256)
+	set(_pb_hz 16000000)
+	set(_pb_eeprom 4096)
+	set(_pb_has_usart1 1)
+else()
+	message(FATAL_ERROR "pureboot: no geometry for ${LIBAVR_MCU}")
+endif()
+set(_pb_slot 512)
+math(EXPR _pb_base "${_pb_flash} - ${_pb_slot}")
+math(EXPR _pb_base_hex "${_pb_base}" OUTPUT_FORMAT HEXADECIMAL)
+# Patched-vector chips hand over through the trampoline word below the slot,
+# which is also the slot's own last word — their budget is slot − 2.
+if(LIBAVR_MCU MATCHES "^atmega" AND NOT LIBAVR_MCU MATCHES "^atmega48")
+	set(_pb_app 0)
+	set(_pb_limit ${_pb_slot})
+else()
+	math(EXPR _pb_app "${_pb_base} - 2")
+	math(EXPR _pb_limit "${_pb_slot} - 2")
+endif()
+
+# simavr names its cores after the base dies; the A revisions run on them
+# (the 644PA on the 644P core).
+set(_pb_sim_mcu ${LIBAVR_MCU})
+if(LIBAVR_MCU MATCHES "^atmega(8|16|32|48|88|164|168|644)a$")
+	string(REGEX REPLACE "a$" "" _pb_sim_mcu ${LIBAVR_MCU})
+elseif(LIBAVR_MCU STREQUAL "atmega644pa")
+	set(_pb_sim_mcu atmega644p)
+endif()
+
+# The function runs in its caller's scope, so everything it needs crosses
+# scopes as global properties.
+set_property(GLOBAL PROPERTY PUREBOOT_BASE_HEX ${_pb_base_hex})
+set_property(GLOBAL PROPERTY PUREBOOT_APP ${_pb_app})
+set_property(GLOBAL PROPERTY PUREBOOT_WRAP "${_pb_wrap}")
+set_property(GLOBAL PROPERTY PUREBOOT_DEFAULT_HZ ${_pb_hz})
+set_property(GLOBAL PROPERTY PUREBOOT_HAS_USART ${_pb_has_usart})
+set_property(GLOBAL PROPERTY PUREBOOT_HAS_USART1 ${_pb_has_usart1})
+
+# The port's own build (tests, the size matrix) reads the geometry from the
+# parent scope; a downstream consumer gets the same variables for free.
+set(PUREBOOT_BASE_HEX ${_pb_base_hex} PARENT_SCOPE)
+set(PUREBOOT_PAGE ${_pb_page} PARENT_SCOPE)
+set(PUREBOOT_SLOT ${_pb_slot} PARENT_SCOPE)
+set(PUREBOOT_LIMIT ${_pb_limit} PARENT_SCOPE)
+set(PUREBOOT_EEPROM ${_pb_eeprom} PARENT_SCOPE)
+set(PUREBOOT_DEFAULT_HZ ${_pb_hz} PARENT_SCOPE)
+set(PUREBOOT_HAS_USART ${_pb_has_usart} PARENT_SCOPE)
+set(PUREBOOT_HAS_USART1 ${_pb_has_usart1} PARENT_SCOPE)
+set(PUREBOOT_SIM_MCU ${_pb_sim_mcu} PARENT_SCOPE)
+
+# The rates a default may pick, fastest first.
+set_property(GLOBAL PROPERTY PUREBOOT_BAUD_LADDER 115200 57600 38400 19200 9600)
+
+# Whether <baud> is reachable from <clock> within 2.5 %, by the same
+# best-of-U2X-and-plain divisor search libavr's solve_baud runs, so a build
+# never trips the compile-time error it is checked against. A software build
+# also needs the polled receiver's 100-cycles-a-bit floor: at low clocks the
+# U2X divisor reaches rates the bit-banged sampler cannot.
+function(pureboot_baud_feasible clock baud software outvar)
+	set(${outvar} 0 PARENT_SCOPE)
+	math(EXPR _cycles "${clock} / ${baud}")
+	if(software AND _cycles LESS 100)
+		return()
+	endif()
+	foreach(divisor 8 16)
+		math(EXPR _step "${divisor} * ${baud}")
+		math(EXPR _n "(${clock} + ${_step} / 2) / ${_step}")
+		if(_n LESS 1 OR _n GREATER 4096)
+			continue()
+		endif()
+		math(EXPR _actual "${clock} / (${divisor} * ${_n})")
+		math(EXPR _delta "${_actual} - ${baud}")
+		if(_delta LESS 0)
+			math(EXPR _delta "-(${_delta})")
+		endif()
+		math(EXPR _error_bp "${_delta} * 10000 / ${baud}")
+		if(_error_bp LESS_EQUAL 250)
+			set(${outvar} 1 PARENT_SCOPE)
+			return()
+		endif()
+	endforeach()
+endfunction()
+
+# The fastest ladder rate the clock reaches.
+function(pureboot_default_baud clock software outvar)
+	get_property(_ladder GLOBAL PROPERTY PUREBOOT_BAUD_LADDER)
+	foreach(baud ${_ladder})
+		pureboot_baud_feasible(${clock} ${baud} ${software} _ok)
+		if(_ok)
+			set(${outvar} ${baud} PARENT_SCOPE)
+			return()
+		endif()
+	endforeach()
+	message(FATAL_ERROR "pureboot: no standard baud rate fits a ${clock} Hz clock within 2.5 % "
+	        "— pass BAUD <rate> to deploy a non-standard one")
+endfunction()
+
+# pureboot_add_loader(<name> [CLOCK <hz>] [BAUD <bd>]
+#                     [SERIAL auto|hardware|software] [USART <n>]
+#                     [RX <pin>] [TX <pin>] [TIMEOUT <s>])
+#
+# The loader target plus its flashable images (<name>.hex for a programmer,
+# <name>.bin for --update-loader). The resolved deployment is stamped on the
+# target as PUREBOOT_HZ / PUREBOOT_BAUD / PUREBOOT_LINK (the link spelled
+# usart0, usart1 or sw:<RX>,<TX>) — what a test harness speaks to it with.
+function(pureboot_add_loader name)
+	cmake_parse_arguments(PB "" "CLOCK;BAUD;SERIAL;USART;RX;TX;TIMEOUT" "" ${ARGN})
+	if(PB_UNPARSED_ARGUMENTS)
+		message(FATAL_ERROR "pureboot_add_loader(${name}): unknown arguments ${PB_UNPARSED_ARGUMENTS}")
+	endif()
+	get_property(_hz GLOBAL PROPERTY PUREBOOT_DEFAULT_HZ)
+	get_property(_base_hex GLOBAL PROPERTY PUREBOOT_BASE_HEX)
+	get_property(_app GLOBAL PROPERTY PUREBOOT_APP)
+	get_property(_wrap GLOBAL PROPERTY PUREBOOT_WRAP)
+	get_property(_usart GLOBAL PROPERTY PUREBOOT_HAS_USART)
+	get_property(_usart1 GLOBAL PROPERTY PUREBOOT_HAS_USART1)
+
+	if(NOT PB_CLOCK)
+		set(PB_CLOCK ${_hz})
+	endif()
+	if(NOT PB_TIMEOUT)
+		set(PB_TIMEOUT 8)
+	endif()
+	if(NOT PB_SERIAL)
+		set(PB_SERIAL auto)
+	endif()
+	if(DEFINED PB_USART AND PB_SERIAL STREQUAL "software")
+		message(FATAL_ERROR "pureboot_add_loader(${name}): USART ${PB_USART} contradicts SERIAL software")
+	endif()
+	if(DEFINED PB_USART)
+		set(PB_SERIAL hardware)
+	elseif(PB_SERIAL STREQUAL "hardware")
+		set(PB_USART 0)
+	endif()
+
+	set(_serial_defines "")
+	if(PB_SERIAL STREQUAL "hardware")
+		if(PB_USART EQUAL 1 AND NOT _usart1)
+			message(FATAL_ERROR "pureboot_add_loader(${name}): ${LIBAVR_MCU} has no USART1")
+		elseif(NOT _usart)
+			message(FATAL_ERROR "pureboot_add_loader(${name}): ${LIBAVR_MCU} has no hardware USART")
+		endif()
+		set(_serial_defines PUREBOOT_USART=${PB_USART})
+		set(_link usart${PB_USART})
+	else()
+		if(PB_SERIAL STREQUAL "auto")
+			if(_usart AND (PB_RX OR PB_TX))
+				message(WARNING "pureboot_add_loader(${name}): RX/TX apply to the software UART, "
+				        "which auto does not pick on ${LIBAVR_MCU} — SERIAL software to force it")
+			endif()
+			if(_usart)
+				set(_link usart0)
+			else()
+				set(PB_SERIAL software)
+			endif()
+		endif()
+		if(PB_SERIAL STREQUAL "software")
+			if(NOT PB_RX)
+				set(PB_RX pb0)
+			endif()
+			if(NOT PB_TX)
+				set(PB_TX pb1)
+			endif()
+			foreach(_pin ${PB_RX} ${PB_TX})
+				if(NOT _pin MATCHES "^p[a-h][0-7]$")
+					message(FATAL_ERROR "pureboot_add_loader(${name}): pin '${_pin}' is not of the form pb1")
+				endif()
+			endforeach()
+			set(_serial_defines PUREBOOT_SOFT_SERIAL PUREBOOT_RX=${PB_RX} PUREBOOT_TX=${PB_TX})
+			# sw:<RX>,<TX> as port letter and bit, upcased.
+			string(SUBSTRING ${PB_RX} 1 2 _rx_pin)
+			string(SUBSTRING ${PB_TX} 1 2 _tx_pin)
+			string(TOUPPER "sw:${_rx_pin},${_tx_pin}" _link)
+			string(REPLACE "SW" "sw" _link ${_link})
+		endif()
+	endif()
+	if(NOT PB_BAUD)
+		if(PB_SERIAL STREQUAL "software")
+			pureboot_default_baud(${PB_CLOCK} 1 PB_BAUD)
+		else()
+			pureboot_default_baud(${PB_CLOCK} 0 PB_BAUD)
+		endif()
+	endif()
+
+	set(_defines PUREBOOT_CLOCK_HZ=${PB_CLOCK} PUREBOOT_BAUD=${PB_BAUD} PUREBOOT_TIMEOUT=${PB_TIMEOUT}
+	    ${_serial_defines})
+
+	add_executable(${name} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pureboot.cpp)
+	target_link_libraries(${name} PRIVATE libavr)
+	target_compile_definitions(${name} PRIVATE ${_defines})
+	# Codegen shaping for the loader TU only, worth 14–36 B depending on the
+	# chip. At -Os GCC otherwise rewrites the byte-stream loops' counters into
+	# end-pointer forms that cost registers (-fno-ivopts,
+	# -fno-split-wide-types), leaves register pressure on the table with the
+	# default allocator (-fira-algorithm=priority), and keeps loop-invariant
+	# immediates and expression temporaries in registers
+	# (-fno-move-loop-invariants, -fno-tree-ter) — but every loop body here
+	# contains a call, so a register held across it costs more than the
+	# load-immediate it saves.
+	target_compile_options(${name} PRIVATE
+	    -fno-ivopts -fira-algorithm=priority -fno-move-loop-invariants -fno-tree-ter -fno-split-wide-types)
+	target_link_options(${name} PRIVATE -nostartfiles -Wl,--section-start=.text=${_base_hex}
+	                    -Wl,--defsym=pureboot_app=${_app} ${_wrap})
+	add_custom_command(TARGET ${name} POST_BUILD COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${name}>)
+	# The ELF is a container, never flashed: .hex for a programmer, .bin (the
+	# slot's bare bytes) for --update-loader.
+	add_custom_command(TARGET ${name} POST_BUILD
+	                   COMMAND ${CMAKE_OBJCOPY} -O ihex -R .eeprom
+	                           $<TARGET_FILE:${name}> $<TARGET_FILE:${name}>.hex
+	                   COMMAND ${CMAKE_OBJCOPY} -O binary -R .eeprom
+	                           $<TARGET_FILE:${name}> $<TARGET_FILE:${name}>.bin)
+	set_target_properties(${name} PROPERTIES PUREBOOT_HZ ${PB_CLOCK} PUREBOOT_BAUD ${PB_BAUD}
+	                      PUREBOOT_LINK ${_link})
+endfunction()

pureboot/README.md

@@ -2,77 +2,132 @@
 
 A serial bootloader on [libavr](https://git.blackmark.me/avr/libavr), pure by
 constraint: one C++ source, no inline assembly, no global register variables
-(attributes allowed), built for **every chip libavr targets — all 37 —
-fitting each chip's smallest boot sector**: 512 bytes everywhere — 488 B on
-the tiny13s, 498–502 B on the tiny25/45/85, 466–504 B across the megas
-(474 B on the boot-section-less m48s, 498 B on the 644s) — except the
-ATmega1284/1284P, whose smallest boot sector is 1 KiB and whose far-flash
-machinery (ELPM reads, RAMPZ page commands, word-addressed wire) lands at
-558 B in a 1 KiB slot: the 512-byte figure is a hardware boundary those
-chips simply do not have, and no implementation of this feature set fits it
-there. The device speaks primitives; every composite — verify, erase,
-reset-vector surgery, updating the loader itself — lives in the host tool
-(`pureboot.py`).
+(attributes and compiler flags allowed), **512 bytes on every chip libavr
+targets — all 37**. The device speaks primitives; every composite — verify,
+erase, reset-vector surgery, updating the loader itself — lives in the host
+tool (`pureboot.py`).
 
 The image is **position-independent**: control flow is PC-relative, the
 read/write paths take wire addresses, the write guard protects the slot the
 code is *running* in (from the runtime return address), the info block is
-addressed from that same anchor, and the application jump is an indirect
-call to an absolute entry. The identical binary therefore runs from any
-slot with every command intact — which makes pureboot **its own staging
-loader**: the host installs the same binary one slot below the resident,
-jumps into it, and lets it rewrite the resident. The slot is 512 bytes
-(1 KiB on the word-addressed large chips, matching their boot-sector
-minimum); on the tinies the budget is 510, not 512: a slot's last word
-belongs to the host-managed trampoline (below).
+addressed from that same anchor, and the application jump is an indirect call
+to an absolute entry. The identical binary therefore runs from any slot with
+every command intact, which makes pureboot **its own staging loader**: the
+host installs the same binary one slot below the resident, jumps into it, and
+lets it rewrite the resident.
 
-## Link
+## Chips
 
-| Chip | Serial | Baud | Clock assumed |
-|---|---|---|---|
-| every ATmega | the hardware USART (USART0), RXD/TXD per pinout | 115200 8N1 | 16 MHz crystal |
-| ATtiny25/45/85 | software UART, RX = PB0, TX = PB1 | 57600 8N1 | 8 MHz internal RC |
-| ATtiny13/13A | software UART, RX = PB0, TX = PB1 | 57600 8N1 | 9.6 MHz internal RC |
+Sizes are the default configuration: the hardware USART0 at 115200 8N1 on a
+16 MHz crystal, or the software UART on RX = PB0 / TX = PB1 at 57600 8N1 on
+the tinies' RC oscillator (9.6 MHz on the t13s, 8 MHz above). Every axis moves
+per build — see *Configuration*; the largest image any of them produces is a
+software UART at a slow baud, which on the 1284s is 494 B, the tightest fit in
+the whole matrix at 18 B spare.
 
-The tiny RX pin has its pull-up enabled; TX idles high. All multi-byte
-quantities on the wire are little-endian.
+| Chip | Flash | Loader at | Link | Size |
+|---|---|---|---|---|
+| ATtiny13, ATtiny13A † | 1 KiB | 0x0200 | software | 416 B |
+| ATtiny25 † | 2 KiB | 0x0600 | software | 420 B |
+| ATtiny45 † | 4 KiB | 0x0e00 | software | 424 B |
+| ATtiny85 † | 8 KiB | 0x1e00 | software | 424 B |
+| ATmega8, 8A | 8 KiB | 0x1e00 | USART0 | 396 B |
+| ATmega16, 16A | 16 KiB | 0x3e00 | USART0 | 400 B |
+| ATmega32, 32A | 32 KiB | 0x7e00 | USART0 | 400 B |
+| ATmega48, 48A, 48P, 48PA † | 4 KiB | 0x0e00 | USART0 | 414 B |
+| ATmega88, 88A, 88P, 88PA | 8 KiB | 0x1e00 | USART0 | 434 B |
+| ATmega168, 168A, 168P, 168PA | 16 KiB | 0x3e00 | USART0 | 438 B |
+| ATmega328, 328P | 32 KiB | 0x7e00 | USART0 | 438 B |
+| ATmega164A, 164P, 164PA | 16 KiB | 0x3e00 | USART0 | 438 B |
+| ATmega324A, 324P, 324PA | 32 KiB | 0x7e00 | USART0 | 438 B |
+| ATmega644, 644A, 644P, 644PA | 64 KiB | 0xfe00 | USART0 | 432 B |
+| ATmega1284, 1284P | 128 KiB | 0x1fe00 | USART0 | 478 B |
+
+† No hardware boot section: the host patches the reset vector, and the budget
+is 510 bytes, since the slot's last word is the trampoline.
+
+The 1284s are the heaviest because they alone carry the far-flash machinery —
+ELPM reads, RAMPZ page commands, a word-addressed wire.
+
+The software UART enables the RX pull-up; TX idles high. All multi-byte wire
+quantities are little-endian.
+
+## Configuration
+
+Every deployment axis is a build parameter of `pureboot_add_loader()` (in
+`pureboot/CMakeLists.txt`) — the one way a loader target is created, by this
+repo's build and by a downstream project alike:
+
+| Argument | Meaning | Default |
+|---|---|---|
+| `CLOCK <hz>` | the clock the board runs | 16 MHz megas, 8 MHz t25/45/85, 9.6 MHz t13s |
+| `BAUD <bd>` | the wire rate | the ladder below |
+| `SERIAL auto\|hardware\|software` | the link backend | `auto`: the hardware USART where the chip has one |
+| `USART <n>` | the USART instance (x4 megas carry two) | 0 |
+| `RX <pin>`, `TX <pin>` | software-UART pins | `pb0`, `pb1` |
+| `TIMEOUT <s>` | the activation window | 8 |
+
+The default baud is the fastest of 115200/57600/38400/19200/9600 the clock
+reaches within 2.5 % — the same U2X-included divisor search libavr's baud
+solver runs — and on a software build additionally within the polled
+receiver's 100-cycles-a-bit floor. Whatever is picked or overridden is
+re-checked in the compile: an infeasible combination, or a USART the chip does
+not have, fails with a named static assert.
+
+A downstream project brings its usual libavr setup (the `libavr` target, the
+chip via the `LIBAVR_MCU` toolchain preset), consumes this directory, and
+states its deployment — an ATmega328P on its shipped 1 MHz fuses with the
+software UART on hand-picked pins, say:
+
+```cmake
+FetchContent_Declare(bootloader GIT_REPOSITORY git@git.blackmark.me:avr/bootloader.git GIT_TAG main)
+FetchContent_MakeAvailable(bootloader)
+add_subdirectory(${bootloader_SOURCE_DIR}/pureboot pureboot)
+
+pureboot_add_loader(myboot CLOCK 1000000 SERIAL software TX pb1 RX pb5)
+```
+
+The function emits the ELF plus `myboot.hex` (the programmer artifact) and
+`myboot.bin` (the self-update image), prints the size, and stamps the resolved
+deployment on the target as the `PUREBOOT_HZ`, `PUREBOOT_BAUD` and
+`PUREBOOT_LINK` properties — what a flashing script or test harness needs to
+speak to the build. This exact deployment runs the full protocol suite in CI
+(`pureboot.custom`).
 
 ## Activation
 
-Reset enters the loader (BOOTRST on the boot-sectioned megas; the patched
-reset vector on the tinies and the boot-section-less m48s) — except a
-watchdog reset, which hands straight to the application (the application
-owns its watchdog; it must clear WDRF itself, which also releases the
-WDRF-forced WDE).
+Reset enters the loader (BOOTRST on the boot-sectioned megas, the patched
+reset vector elsewhere) — except a watchdog reset, which hands straight to the
+application, since the application owns its watchdog and must clear WDRF
+itself.
 
-The host then has one activation window per awaited byte to knock: `p` then
-`b`. Each awaited byte gets a fresh window; any other byte is discarded and
-awaited again (line noise cannot lock the loader, only delay it). A window
-expiring with an idle line boots the application.
+The host then knocks `p` then `b`, each awaited byte under a fresh activation
+window; any other byte is discarded and awaited again, so line noise can delay
+the loader but never lock it. A window expiring on an idle line boots the
+application.
 
-The window length is a compile-time constant — 8 s by default, another value
-via the `PUREBOOT_TIMEOUT` CMake cache variable — so the whole EEPROM belongs
-to the application; pureboot never uses it for its own state. Re-timing a
-deployed loader is a self-update with a re-timed build (below).
+The window is a compile-time constant (`TIMEOUT`, 8 s by default), so the whole
+EEPROM belongs to the application — pureboot keeps no state of its own.
+Re-timing a deployed loader is a self-update with a re-timed build.
 
 ## Session
 
 After the knock the loader stays in its command loop until `J` jumps away or
 the chip resets. Before reading each command it waits for any pending EEPROM
-write to finish and sends the prompt `+` (0x2b) — the prompt is therefore
-also the completion ack of the previous command. A session is: await `+`,
-send a command, read its reply, repeat.
+write and sends the prompt `+` (0x2b), which is therefore also the previous
+command's completion ack. A session is: await `+`, send a command, read its
+reply, repeat.
 
 On chips whose flash exceeds 64 KiB (the 1284s — info-block flag bit 1) the
 `R`/`W` flash addresses are **word** addresses; everywhere else they are byte
-addresses (the 644s' 64 KiB is exactly the 16-bit byte space and stays
-byte-addressed). EEPROM addresses are always bytes, counts always bytes.
+addresses (the 644s' 64 KiB is exactly the 16-bit byte space). EEPROM
+addresses and all counts are bytes.
 
 | Cmd | Arguments | Reply |
 |---|---|---|
 | `b` | — | the 12-byte info block |
 | `R` | addr16, n8 | n flash bytes (n = 0 means 256) |
-| `W` | addr16, then one page of data | — (completion = next prompt) |
+| `W` | addr16 (any address in the page), then one page of data | — (completion = next prompt) |
 | `r` | addr16, n8 | n EEPROM bytes (n = 0 means 256) |
 | `w` | addr16, n8, then n data bytes | `+` per byte, sent once its write has begun |
 | `F` | — | 4 bytes: low fuse, lock, extended fuse, high fuse |
@@ -80,72 +135,74 @@ byte-addressed). EEPROM addresses are always bytes, counts always bytes.
 | other | — | ignored; the loop re-prompts (send a junk byte, await `+`, to resync) |
 
 `W` streams exactly one SPM page (size from the info block) into the buffer,
-then erases and programs; the address must be page-aligned. Pages inside the
-512-byte slot the loader is *running* in are drained but never programmed — a
-broken host cannot brick the running copy, and a staged copy may rewrite the
-resident slot. `w` is host-paced: send the next byte only after the previous
-byte's `+`. `F` returns the bytes in the hardware's Z order; on a chip
-without an extended fuse byte (the ATtiny13A) that slot carries no meaning.
-Fuse *writing* does not exist: SPM reaches flash (and, on the mega, lock
-bits) only — fuse bytes are external-programming territory by hardware.
+then erases and programs — except pages inside the 512-byte slot
+the loader is *running* in, which are drained and left alone, so a broken host
+cannot brick the running copy and a staged copy may rewrite the resident.
 
-`J` is the one control-transfer primitive: the host uses it to run the
-application (word 0 on the mega, the trampoline word on the tinies — both
-known from the info block) and to move between loader copies during a
-self-update. A jump to a loader slot's base re-enters that copy's own
-startup; it must then be knocked afresh.
+The loader never clears the SPM buffer before a fill, so **one `W` may program
+the wrong bytes, and the host is what fixes it**. The buffer is write-once per
+word until cleared, and two things leave words in it: a refused page, and —
+where SPM runs from anywhere, the tinies and the m48s — an application that
+self-programmed before entering. The next `W` takes those stale words and
+clears them, since a page write auto-erases the buffer (§26.2.1; §19.2 on the
+tinies), so repeating it programs correctly. The host therefore verifies every
+page it writes and rewrites what comes back wrong (three retries, then it
+stops).
+
+`w` is host-paced: send the next byte only after the previous byte's `+`. `F`
+returns the bytes in the hardware's Z order; on a chip without an extended
+fuse byte that slot carries no meaning. Fuse *writing* does not exist — SPM
+reaches flash and boot lock bits only.
+
+`J` is the one control-transfer primitive: it runs the application (word 0 or
+the trampoline word, both known from the info block) and moves between loader
+copies during a self-update. A jump to a slot's base re-enters that copy's own
+startup, which must then be knocked afresh.
 
 The info block (`b`):
 
 | Offset | Content |
 |---|---|
-| 0–2 | `'P'`, `'B'`, protocol version (1) |
+| 0–2 | `'P'`, `'B'`, pureboot version (3) |
 | 3–5 | device signature |
 | 6 | SPM page size in bytes (0 means 256) |
 | 7–8 | loader base — application flash ends here (a word address when bit 1 is set) |
 | 9–10 | EEPROM size |
 | 11 | bit 0: host must patch the reset vector (no hardware boot section); bit 1: flash wire addresses are word addresses |
 
-Composites are the host's job: verify = read back and compare, erase =
-write `0xff` (per page for flash, per byte for EEPROM).
+## Version
+
+The info block's third byte is the **pureboot version** — the loader's one
+identity number, and the only way to tell what a deployed loader is. Nothing
+else is numbered: the wire protocol has no version, a pureboot version implies
+it, and the host tool holds that map. The tool states the window of loader
+versions it speaks (`OLDEST_LOADER`/`NEWEST_LOADER` in `pureboot.py`), and a
+version that changes the protocol becomes the new floor there. None has so
+far: 1 through 3 speak the identical session. A loader newer than the tool is
+refused by name rather than decoded on the assumption that nothing moved.
+
+The tool carries its own version, free to drift; `--version` prints it and the
+window.
 
 ## Deployment
 
 The build leaves three artifacts per chip. The ELF is a container for the
-tests and objcopy — never flashed. The **.hex is the programmer artifact**:
-it carries its own addresses and lands the loader in its top slot,
-touching nothing else. The **.bin is the self-update image** — the slot's
-bare bytes with no addressing, which a programmer would put at address 0.
-On a boot-sectioned mega a copy at 0 is dead weight (SPM only executes
-from the boot section, so it cannot even heal itself — reflash the .hex);
-on the patched-vector chips it *runs* (the image is position-independent
-and reset enters word 0), reports its canonical geometry, and the ordinary
-`--update-loader` flow re-homes a build into the top slot from any
-position — the staging install and the word-0 redirect execute from
-copies outside page 0's slot, and a copy sitting in the staging slot
-itself is recognized as the installed staging copy and left in place (it
-streams the new resident like any staged copy, so an older build installs
-a newer one). `pureboot.rehome` is the acceptance test for both
-positions. Flashing the application afterwards overwrites the stale copy,
-vector surgery included.
+tests and objcopy, never flashed. The **.hex is the programmer artifact**: it
+carries its own addresses and lands the loader in its top slot, touching
+nothing else. The **.bin is the self-update image** — the slot's bare bytes.
 
-**Boot-sectioned megas**: program the loader at `flash − slot` with an
-external programmer. Every such mega has a BOOTSZ step whose boot section
-is exactly the loader slot — 512 B, the second-smallest step on the 8 KiB
-and 16 KiB chips (m8, m88, m16, m168, m164), the smallest on the 32 KiB
-ones (m32, m328, m324); on the 1284s that step is the smallest, 512 words,
-which is why their slot is 1 KiB — so the ATmega328P profiles below apply
-to every one of them with its own addresses and slot size; the per-chip
-BOOTSZ ladders live in the host tool (`BOOT_FUSE`). The 1284s' numbers:
-standalone = BOOTSZ 512 words (reset at the loader base 0x1fc00);
-self-update = 1024 words, covering both 1 KiB slots, the loader-first
-reset landing at 0x1f800 — the staging slot, walked across when erased.
+**Boot-sectioned megas**: program the loader at `flash − 512` with an external
+programmer. Every such mega has a BOOTSZ step whose boot section is exactly
+the 512-byte slot — the second-smallest step on the 8 KiB and 16 KiB chips,
+the smallest on the 32 KiB ones — so the ATmega328P profiles below apply to
+every one of them with its own addresses; the per-chip BOOTSZ ladders live in
+the host tool (`BOOT_FUSE`).
 
-The **644s** are the geometry's sweet spot: their smallest boot section
-(512 words = 1 KiB) is exactly *two* 512-byte slots, so the resident and
-its staging slot both live inside the minimum section — self-update needs
-no fuse step up, and the standalone profile does not exist (reset lands at
-0xfc00, one erased slot below the loader: the loader-first walk built in).
+The **644s and 1284s** are the geometry's sweet spot: their smallest boot
+section (512 words = 1 KiB) is exactly *two* slots, so the resident and its
+staging slot both live inside the minimum section. Self-update needs no fuse
+step up, and the standalone profile does not exist — reset lands one erased
+slot below the loader (0xfc00 / 0x1fc00) and walks up into it.
 
 ATmega328P profiles (addresses for its 32 KiB):
 
@@ -155,116 +212,142 @@ ATmega328P profiles (addresses for its 32 KiB):
 | 512 words (1 KB) | unprogrammed | *Self-update, app-first*: reset always boots the application, which owns all 31.5 KB and must offer its own jump to 0x7e00 to reach the loader (a virgin chip reaches it by reset across erased flash). Updates are power-fail-safe except mid-rewrite of the resident slot itself (no reset path leads to the staging copy then). |
 | 512 words (1 KB) | programmed | *Self-update, loader-first*: reset lands at 0x7c00 — the staging slot, normally erased, so execution walks up into the loader; during an update it is the staging copy itself, so a mid-rewrite power loss recovers by reset. The loss windows move to the staging install/retire page writes instead (page-write scale). The host keeps `[0x7c00, 0x7e00)` clear of application data (`--force` overrides). |
 
-Applications are flashed unmodified — word 0 stays the application's own
+Applications are flashed unmodified here — word 0 stays the application's own
 reset vector, and the hand-over jumps to 0.
 
-**Patched-vector chips — the tinies and the m48s** (no boot section; the
-m48s' SPM runs from the entire flash, Atmel-8271 §26): program the loader
-at `flash − 512`; erased flash below it walks up into the loader, so a
-virgin chip activates. When flashing an application the host performs
-reset-vector surgery: word 0 is rewritten to `rjmp` to the loader base, and
-the application's own entry is re-encoded as a trampoline `rjmp` in the
-word just below the loader (`base − 2`, where the hand-over jumps). Every
-other vector stays the application's. The patched page 0 and the trampoline
-page are written *first*, so from the first write on an interrupted flash
-still resets into the loader; an erase runs top-down for the same reason.
-The m48s speak this profile over their hardware USART — no fuse preflight,
-BOOTRST does not exist there.
+**Patched-vector chips — the tinies and the m48s** (no boot section; the m48s'
+SPM runs from the entire flash, Atmel-8271 §26): program the loader at
+`flash − 512`; erased flash below it walks up into the loader, so a virgin
+chip activates. Flashing an application then takes reset-vector surgery: word
+0 becomes an `rjmp` to the loader base, and the application's own entry is
+re-encoded as a trampoline `rjmp` in the word just below the loader
+(`base − 2`, where the hand-over jumps). Every other vector stays the
+application's. The patched page 0 and the trampoline page are written *first*
+and an erase runs top-down, so from the first write on an interruption still
+resets into the loader.
+
+A .bin programmed at address 0 by mistake is dead weight on a boot-sectioned
+mega (SPM only executes from the boot section — reflash the .hex), but *runs*
+on a patched-vector chip, and the ordinary `--update-loader` flow re-homes it
+into the top slot from there (`pureboot.rehome`).
 
 ## Updating the loader
 
 `pureboot.py --update-loader new_pureboot.bin` replaces the resident loader
-with any pureboot build — a re-timed window, a newer protocol — using the
+with any pureboot build — a re-timed window, a newer version — using the
 loader itself as its own staging loader. The image is the loader's own 512
-bytes as a raw binary, or the Intel HEX the build emits beside it, which
-links the loader at its base inside an otherwise blank flash image:
+bytes as a raw binary, or the Intel HEX the build emits beside it.
 
-The preflight refuses an image built for another chip: the info block
-embedded in every pureboot binary (signature, page size, loader base,
-EEPROM size, flags) must match the device's own, and the error names both.
-Die revisions share their base signature and geometry, so their images are
-interchangeable — as the silicon is. `loader_image()` also accepts a
-padded image (a raw .bin padded from 0, or a whole-flash read-back with
-the loader resident) and peels it to the slot content by the embedded base.
+The preflight refuses an image built for another chip: the info block embedded
+in every pureboot binary (signature, page size, loader base, EEPROM size,
+flags) must match the device's own, and the error names both. Die revisions
+share their base signature and geometry, so their images are interchangeable —
+as the silicon is.
 
-1. The staging slot `[base−slot, base)` is saved to a host-side state file
-   (on the 1 KB tiny13s that is the whole application, vectors included).
-2. The resident installs the identical update image there. On the
-   patched-vector chips the host composes the slot's last word — the same
-   address as the resident's trampoline — as a jump to the resident base,
-   so even an abandoned staging copy times out into a loader, never into
-   garbage. A loader already sitting whole in the staging slot (its info
-   block in place, the slot unchanged since the update began) is left as
-   the staging copy instead — rewriting it would only meet its own
-   running-slot guard.
-3. `J` enters the staging copy, which rewrites the resident slot. On the
-   patched-vector chips whose staging slot sits away from page 0 the host
-   first re-aims word 0 at the staging copy, so a power loss mid-rewrite
-   still resets into a loader; on the tiny13s the staging slot carries the
-   reset vector itself.
+1. The staging slot `[base−512, base)` is saved to a host-side state file (on
+   the 1 KB tiny13s that is the whole application, vectors included).
+2. The resident installs the update image there. On the patched-vector chips
+   the host composes the slot's last word as a jump to the resident base, so
+   even an abandoned staging copy times out into a loader. A loader already
+   sitting whole in the staging slot is left as the staging copy instead —
+   rewriting it would only meet its own running-slot guard.
+3. `J` enters the staging copy, which rewrites the resident slot. Where a
+   patched reset vector routes through the resident, the host first re-aims
+   word 0 at the staging copy, so a power loss mid-rewrite still resets into a
+   loader; on the tiny13s the staging slot carries the reset vector itself.
 4. `J` enters the new resident, which restores the staging slot's saved
-   content (word 0 and the trampoline with it) and the state file is
-   discarded.
+   content, and the state file is discarded.
 
-Every phase is idempotent and keyed off the actual flash state: re-running
-the same command after any interruption resumes and completes. The state
-file carries the only bytes not recoverable from the device; if it is lost
-mid-update the update still completes, and the staging region is restored by
-reflashing the application. A boot-sectioned mega needs its fuses for the
-preflight (BOOTSZ gate, profile notes) — read from the device, or supplied
-with `--assume-fuses` where reading is impossible (simulators); the
-patched-vector chips need none.
+Every phase is idempotent and keyed off the actual flash state, so re-running
+the same command after any interruption resumes and completes. The state file
+carries the only bytes not recoverable from the device; losing it mid-update
+still completes the update, and the staging region comes back by reflashing
+the application. A boot-sectioned mega needs its fuses for the preflight — read
+from the device, or supplied with `--assume-fuses` where reading is impossible
+(simulators).
 
 ## Host tool
 
 `pureboot.py` — Python 3, standard library only. The port layer is the one
-platform-specific part: termios drives any tty on POSIX (a USB adapter as
-well as a simavr pty), the Win32 serial API through `ctypes` drives a COM
-port on Windows (`--port COM6`; the `\\.\` form for two-digit ports is
-supplied by the tool). Opening the port asserts DTR and RTS on both, so a
-board that wires DTR to reset gets its reset pulse and opens the activation
-window by itself.
+platform-specific part: termios drives any tty on POSIX (a USB adapter as well
+as a simavr pty), the Win32 serial API through `ctypes` drives a COM port on
+Windows (`--port COM6`; the `\\.\` form for two-digit ports is supplied by the
+tool). Opening the port asserts DTR and RTS on both, so a board that wires DTR
+to reset gets its reset pulse and opens the activation window by itself.
 
     pureboot.py --port /dev/ttyUSB0 --baud 57600 \
         --info --fuses --flash app.hex
 
 Operations run in a fixed order within one session: info, fuses, loader
-update, flash (erase / program / read / verify), EEPROM (erase / program /
-read / verify) — then the loader hands over to the application; `--stay`
-keeps the session alive instead, and a later invocation reconnects into it
-(the knock converges there too). `--flash` and `--eeprom` verify by
-read-back unless `--no-verify`; images are raw binary, or Intel HEX by
-extension. `--force` overrides the refusable safety checks (today: flashing
-application data into a mega's reset walk region).
+update, flash (erase / program / read / verify), EEPROM (the same) — then the
+loader hands over to the application. `--stay` keeps the session alive
+instead, and a later invocation reconnects into it. `--flash` and `--eeprom`
+verify by read-back unless `--no-verify`, and a flash page that reads back
+wrong is rewritten up to three times before the run stops (see `W` above).
+`--verify-flash` only reports. Images are raw binary, or Intel HEX by
+extension. `--force` overrides the refusable safety checks — today, flashing
+application data into a mega's reset walk region.
+
+Readouts come one fact per line: `--info` decodes the info block field by
+field, `--fuses` each fuse byte plus, on a boot-sectioned mega, its decoded
+meaning. Transfers that take wire time draw a transient progress bar on stderr
+when it is a tty. `-v`/`--verbose` adds the decisions as they happen: knock
+counts, the programming plan, update state handling and per-phase page counts.
 
 ## Tests
 
+`tools/check.sh` runs every chip's workflow (`--full` adds the reflect-mode
+builds of libavr's spot set; `tools/make_presets.py` regenerates the presets).
 Per chip preset, `ctest` runs:
 
-- `pureboot.size` — the 510-byte (tinies) / 512-byte (mega) budget;
-- `pureboot.pi` — the position-independence lint: no absolute `jmp`/`call`
-  in the image, the info block within its first 256 bytes;
-- `pureboot.planner` — the host tool's pure logic: programming orders and
-  their recovery properties, the surgery, the staging composition, the
-  boot-fuse decode, and the update preflight's error/warning matrix over
-  synthetic fuse bytes;
+- `pureboot.size` — the 510-byte (patched-vector) / 512-byte budget;
+- `pureboot_*.size` — the size matrix: the serial backends × the clock ladder
+  (1/8/16 MHz; the t13s' own RC menu), the USART1 instance across that same
+  ladder on the x4 chips, and `pureboot_sw_wide`, the slowest ladder rate at
+  the fastest clock — where a software UART's per-bit spin outgrows its
+  one-register delay loop and takes the 16-bit one. That is the largest image
+  the configuration space produces, and a shape the ladder default (always the
+  *fastest* rate a clock reaches) never picks. Pins are immediate operands and
+  the timeout is a constant: neither is an axis;
+- `pbm_*.size` — under `--full`, the exhaustive cross product replacing that
+  compact matrix: every plausible oscillator (the internal ones, the CKDIV8
+  floor, the plain and the UART crystals) × every rate reachable from it ×
+  every backend, unreachable combinations dropping out rather than aborting
+  the configure. Bounded to one chip per size-bearing class — flash
+  addressing, hand-over shape, page size, USART inventory — since everything
+  else in the image is chip-independent code;
+- `pureboot.pi` — the position-independence lint: no absolute `jmp`/`call`, the
+  info block within the image's first 256 bytes;
+- `pureboot.planner` — the host tool's pure logic: programming orders and their
+  recovery properties, the surgery, the staging composition, the boot-fuse
+  decode, the update preflight over synthetic fuse bytes, and the repairing
+  verify against a fake device;
 - `pureboot.protocol` — end to end against a simavr device
-  (`test/pureboot_device.c` — the mega's USART as a pty; on the tinies a
-  cycle-timed GPIO⇄pty bridge for the software UART, plus the SPM/NVM module
-  simavr's tiny cores lack) driven by the real host tool through
-  knock-from-reset, program + verify of both memories, session reconnect, an
-  external reset through the patched vector, and the hand-over to a fixture
-  application whose banner proves the launch — cross-checked against the
-  simulator's ground-truth memory dumps and an independent decode of the
-  surgery's rjmp words;
-- `pureboot.reloc` — the identical image installed one slot below the
-  resident serves the complete command set from there (the
-  position-independence acceptance test);
-- `pureboot.update` — the full `--update-loader` flow to a re-timed build,
-  then every power-fail phase: the device is killed mid-write, restarted
-  from its flash dump, and a re-run must complete the update with the
-  application intact throughout.
+  (`test/pureboot_device.c`: a hardware USART as a pty, or a cycle-timed
+  GPIO⇄pty bridge for a software-UART build, plus the SPM/NVM module simavr's
+  tiny cores lack) driven by the real host tool through knock-from-reset,
+  program + verify of both memories, session reconnect, an external reset
+  through the patched vector, and the hand-over to a fixture application whose
+  banner proves the launch — cross-checked against the simulator's
+  ground-truth memory dumps and an independent decode of the surgery;
+- `pureboot.reloc` — the identical image one slot below the resident serves the
+  complete command set from there;
+- `pureboot.rehome` (t85) — a loader programmed at address 0 or in the staging
+  slot re-homes into the top slot through the ordinary update flow;
+- `pureboot.custom` (328P) — the configuration example's 1 MHz software-serial
+  build driving the full protocol suite, proving the plumbing produces a
+  working loader and not just one that fits;
+- `pureboot.usart1` (644A) — the same suite over the second hardware USART:
+  instance selection is compile-checked everywhere, but only a live session
+  proves the loader polls the USART it claims;
+- `pureboot.dirty` (328P) — entering the loader from a running application over
+  an SPM buffer it deliberately dirtied, the case the loader declines to guard:
+  a bare verify must see the corruption and the repairing verify must fix it in
+  one rewrite. Hardware forbids the state here, but simavr dispatches SPM from
+  anywhere, which is what makes the path constructible;
+- `pureboot.update` — the full `--update-loader` flow, then every power-fail
+  phase: the device is killed mid-write, restarted from its flash dump, and a
+  re-run must complete the update with the application intact.
 
-`size`, `pi`, and `planner` are host logic and run anywhere; the three
-simulator-driven targets need simavr and a pty, so they are POSIX-only —
-on Windows the tool is exercised against real hardware.
+`size`, `pi` and `planner` are host logic and run anywhere; the
+simulator-driven targets need simavr and a pty, so they are POSIX-only.

pureboot/pureboot.cpp

@@ -1,28 +1,14 @@
-// pureboot — a serial bootloader on libavr, pure by constraint: one C++
-// source with no inline assembly and no global register variables, built for
-// every chip libavr targets, 512 bytes on each. The device speaks primitives
-// — read/program flash, read/write EEPROM, fuse bytes, an info block, a jump
-// — and everything composite (verify, erase, reset-vector surgery, updating
-// the loader itself) lives in the host tool. Protocol reference: README.md
-// next to this file.
+// pureboot — a serial bootloader on libavr: one C++ source, no inline
+// assembly, no global register variables, 512 bytes on every chip libavr
+// targets. The device speaks primitives; every composite (verify, erase,
+// reset-vector surgery, self-update) lives in the host tool. Protocol,
+// deployment and configuration: README.md next to this file.
 //
-// The image is position-independent: control flow is PC-relative, the write
-// and read paths take wire addresses, the write guard refuses the 512-byte
-// slot the code is *running* in (taken from the runtime return address), the
-// info block is read relative to that same anchor, and the application jump
-// is an indirect call to an absolute entry. The identical binary therefore
-// runs from any 512-byte slot with every command intact: flashed one slot
-// below the resident loader it becomes the staging loader that rewrites the
-// resident — how pureboot updates itself, host-driven, with no other
-// firmware involved.
-//
-// Entry: reset lands in avr::startup::entry below (BOOTRST on the
-// boot-sectioned megas; the patched reset vector — or erased flash walking
-// up into the loader — on the tinies and the boot-section-less m48s). A
-// watchdog reset hands straight to the application. Otherwise the
-// host has one activation window per awaited knock byte ("pb"); an idle line
-// boots the application. A session then stays in the command loop until 'J'
-// jumps away or the chip resets.
+// The image is position-independent — PC-relative control flow, wire
+// addresses in, the write guard and the info block both anchored on the
+// runtime return address — so the identical binary runs from any slot. That
+// is what makes a copy one slot below able to rewrite the resident one, and
+// every change here has to keep it (test/check_pi.py).
 
 #include <libavr/libavr.hpp>
 
@@ -33,27 +19,21 @@ namespace ee = avr::eeprom;
 namespace pureboot {
 namespace {
 
-// Purely polled — interrupts stay off, every guard folds to nothing.
+// Purely polled: every interrupt guard folds to nothing.
 constexpr auto off = avr::irq::guard_policy::unused;
 
 constexpr std::uint8_t ack = '+';
 
-// Per-chip personality: the clocks the dogfood boards run (16 MHz crystal on
-// the mega, calibrated RC on the tinies). The device signature comes straight
-// from the chip database (avr::hw::db.signature) — compile-time data is the
-// only universal source, since the tiny13A cannot even read its signature row
-// from code.
-consteval avr::hertz_t clock()
-{
-	auto name = std::string_view{avr::hw::db.name};
-	if (name.starts_with("ATtiny13"))
-		return 9.6_MHz;
-	if (name.starts_with("ATtiny"))
-		return 8_MHz;
-	return 16_MHz;
-}
+// Deployment parameters come from the build (pureboot_add_loader()). The
+// signature is not one of them: the chip database is the only universal
+// source — a tiny13A cannot read its own signature row from code.
+#if !defined(PUREBOOT_CLOCK_HZ) || !defined(PUREBOOT_BAUD)
+#error \
+    "PUREBOOT_CLOCK_HZ and PUREBOOT_BAUD select this build's clock and baud — create loader targets with pureboot_add_loader() (README.md)"
+#endif
 
-using dev = avr::device<{.clock = clock()}>;
+using dev = avr::device<{.clock = avr::hertz_t{PUREBOOT_CLOCK_HZ}}>;
+constexpr avr::baud_t wire_baud{PUREBOOT_BAUD};
 
 // The watchdog reset flag's home: MCUSR, or the classic megas' MCUCSR.
 consteval std::int16_t wdrf_field()
@@ -62,90 +42,69 @@ consteval std::int16_t wdrf_field()
 	return avr::hw::db.field_index(reg, "WDRF");
 }
 
-// Geometry: the resident loader owns the top slot of flash — 512 bytes,
-// except on the >64 KiB chips whose own smallest boot sector is 1 KiB (the
-// 1284s): there the slot is 1 KiB, matching the hardware boundary the
-// 512-byte figure comes from everywhere else. The word below the slot is
-// the trampoline (the application's relocated reset vector) on chips
-// without a hardware boot section — the tinies and the m48s, whose SPM
-// runs from anywhere (Atmel-8271 §26). A boot section also means the CPU
-// runs on while the RWW section programs; everywhere else it halts through
-// the operation. The m48s still carry RWWSRE as their temporary-buffer
-// discard (§26.2), so the discard picks by that bit, not by the section.
-constexpr std::uint16_t slot_bytes = spm::flash_bytes > 65536 ? 1024 : 512;
+// The loader owns the top 512 bytes; a staging copy goes in the slot below.
+// Chips without a hardware boot section — the tinies and the m48s, whose SPM
+// runs from anywhere (Atmel-8271 §26) — keep the application's relocated
+// reset vector in the word under the slot.
+constexpr std::uint16_t slot_bytes = 512;
 constexpr std::uint32_t base = spm::flash_bytes - slot_bytes;
 constexpr std::uint16_t page = spm::page_bytes;
 constexpr bool boot_section = avr::hw::curated::has_boot_section();
-constexpr bool rww_discard = spm::detail::has_rww();
 
-// Past 64 KiB a byte address no longer fits the wire's 16 bits, so on the
-// large chips every flash address on the wire — and all slot arithmetic —
-// is a word address instead ('J' always was one). A slot spans the same
-// wire-high-byte pair in either unit (512 B = 2 x 256 bytes, 1 KiB =
-// 2 x 256 words), so the slot index is the high byte with its low bit
-// dropped everywhere.
+// Past 64 KiB a byte address no longer fits the wire's 16 bits, so flash
+// addresses there are word addresses ('J' always was one). A slot is 256 of
+// those — one value of a wire address's high byte, where 512 bytes span two.
 constexpr bool word_flash = spm::flash_bytes > 65536;
 constexpr std::uint16_t wire_base =
     word_flash ? static_cast<std::uint16_t>(base / 2) : static_cast<std::uint16_t>(base);
-constexpr std::uint16_t wire_page_mask = word_flash ? (page / 2 - 1) : (page - 1);
 
-// The activation window, in seconds, is a compile-time constant (the build
-// may override it): the whole EEPROM belongs to the application, and
-// re-timing the loader is a bootloader self-update with a re-timed binary.
+// A compile-time window, so the whole EEPROM belongs to the application;
+// re-timing a deployed loader is a self-update with a re-timed build.
 #if !defined(PUREBOOT_TIMEOUT)
 #define PUREBOOT_TIMEOUT 8
 #endif
 constexpr std::uint8_t timeout_seconds = PUREBOOT_TIMEOUT;
 
-// The 12-byte info block the host reads with the 'b' command; flash-resident
-// (there is no crt to copy a .data image), word-aligned so its wire (word)
-// address is exact on the large chips. The page byte is the wire count
-// convention: 0 means 256.
-[[gnu::progmem]] alignas(2) inline constexpr std::array<std::uint8_t, 12> info_data = {
-    'P',
-    'B',
-    1, // magic, protocol version
-    avr::hw::db.signature[0],
-    avr::hw::db.signature[1],
-    avr::hw::db.signature[2],
-    static_cast<std::uint8_t>(page),
-    wire_base & 0xff,
-    wire_base >> 8, // app flash ends here; resident loader base (a word address on large chips)
-    avr::hw::db.mem.eeprom_size & 0xff,
-    avr::hw::db.mem.eeprom_size >> 8,
-    // bit 0: host must patch the reset vector (no hardware boot section);
-    // bit 1: flash wire addresses are word addresses
-    static_cast<std::uint8_t>((boot_section ? 0 : 1) | (word_flash ? 2 : 0)),
-};
+// The loader's one identity number. The protocol carries none of its own —
+// a version implies it, and the host tool holds that map (README.md).
+constexpr std::uint8_t version = 3;
 
-// The serial link: the hardware USART where the chip has one, the polled
-// software UART (no vector — the table belongs to the application) on PB0/PB1
-// elsewhere. Both are class templates on the clock so only the selected
-// backend is ever instantiated. pending() is the cheap line test the
-// activation window polls; rx() then picks the byte up; drain() holds until
-// the last transmitted frame is fully on the wire (the jump hand-over must
-// not let the target's re-init clip the ack).
-template <avr::hertz_t C>
-consteval std::int16_t rxc_field()
-{
-	return avr::uart::detail::ufield<'0', "UCSR#A", "RXC#">();
-}
+// The 'b' reply, byte for byte (layout: README.md). Flash-resident because
+// no crt copies a .data image — and flash_table's storage carries the word
+// alignment 'b' needs to halve the address on the large chips.
+inline constexpr avr::flash_table<std::array<std::uint8_t, 12>{
+    'P', 'B', version, avr::hw::db.signature[0], avr::hw::db.signature[1], avr::hw::db.signature[2],
+    static_cast<std::uint8_t>(page), // 0 means 256
+    wire_base & 0xff, wire_base >> 8, avr::hw::db.mem.eeprom_size & 0xff, avr::hw::db.mem.eeprom_size >> 8,
+    static_cast<std::uint8_t>((boot_section ? 0 : 1) | (word_flash ? 2 : 0)), // patch-vector, word-addressed
+}>
+    info_data;
 
-template <avr::hertz_t C>
-consteval std::int16_t txc_field()
-{
-	return avr::uart::detail::ufield<'0', "UCSR#A", "TXC#">();
-}
-
-template <avr::hertz_t C>
-consteval std::int16_t status_reg()
-{
-	return avr::uart::detail::ureg<'0', "UCSR#A">();
-}
+// The serial link, per the build's PUREBOOT_USART / PUREBOOT_SOFT_SERIAL,
+// defaulting to the chip's USART0 where it has one. The software receiver is
+// the polled one: the vector table belongs to the application. Templates on
+// the clock, so only the selected backend instantiates. pending() is the
+// cheap line test the activation window polls; drain() holds until the last
+// frame is off the wire, so a hand-over cannot let the target's re-init clip
+// the ack.
+#if defined(PUREBOOT_SOFT_SERIAL) && defined(PUREBOOT_USART)
+#error "PUREBOOT_SOFT_SERIAL and PUREBOOT_USART select opposing serial backends"
+#endif
+#if !defined(PUREBOOT_RX)
+#define PUREBOOT_RX pb0
+#endif
+#if !defined(PUREBOOT_TX)
+#define PUREBOOT_TX pb1
+#endif
+#if defined(PUREBOOT_USART)
+constexpr char usart_digit = '0' + PUREBOOT_USART;
+#else
+constexpr char usart_digit = '0';
+#endif
 
 template <avr::hertz_t C>
 struct hardware_link {
-	using uart = avr::uart::usart0<C, {.baud = 115200_Bd, .max_baud_error = 2.5_pct}>;
+	using uart = avr::uart::usart<usart_digit, C, {.baud = wire_baud, .max_baud_error = 2.5_pct}>;
 
 	// The compiled idle poll: lds UCSR0A (2), sbrc skipping the exit (2),
 	// sbiw + sbci + sbci + brne (6).
@@ -158,7 +117,7 @@ struct hardware_link {
 
 	static bool pending()
 	{
-		return avr::hw::field_impl<rxc_field<C>()>::test();
+		return uart::rx_ready();
 	}
 
 	static std::uint8_t rx()
@@ -173,22 +132,14 @@ struct hardware_link {
 
 	static void drain()
 	{
-		// write() leaves the byte draining behind it. Clear a stale TXC0
-		// first (W1C by writing the sampled status back — the store a hand
-		// assembler writes, keeping U2X0), then wait for the fresh
-		// completion; with a byte still ahead in the shifter TXC0 cannot
-		// re-set until the last pending byte has fully left.
-		using status = avr::hw::reg_impl<status_reg<C>()>;
-		status::write(status::read());
-		while (!avr::hw::field_impl<txc_field<C>()>::test()) {
-		}
+		uart::drain();
 	}
 };
 
 template <avr::hertz_t C>
 struct software_link {
-	using rx_t = avr::uart::software_rx_polled<C, avr::pb0, 57600_Bd>;
-	using tx_t = avr::uart::software_tx<C, avr::pb1, 57600_Bd>;
+	using rx_t = avr::uart::software_rx_polled<C, avr::PUREBOOT_RX, wire_baud>;
+	using tx_t = avr::uart::software_tx<C, avr::PUREBOOT_TX, wire_baud>;
 
 	// The compiled idle poll: sbis skipping the exit (2), sbiw + sbci +
 	// sbci + brne (6).
@@ -201,7 +152,7 @@ struct software_link {
 
 	static bool pending()
 	{
-		return !avr::io::input<avr::pb0>::read(); // a start bit has begun
+		return rx_t::start_pending();
 	}
 
 	static std::uint8_t rx()
@@ -220,15 +171,20 @@ struct software_link {
 	}
 };
 
-using link = std::conditional_t<avr::hw::db.has_instance("USART0") || avr::hw::db.has_instance("USART"),
-                                hardware_link<dev::clock>, software_link<dev::clock>>;
+#if defined(PUREBOOT_USART)
+static_assert(avr::uart::has_usart<usart_digit>(), "PUREBOOT_USART selects a hardware USART this chip does not have");
+using link = hardware_link<dev::clock>;
+#elif defined(PUREBOOT_SOFT_SERIAL)
+using link = software_link<dev::clock>;
+#else
+using link =
+    std::conditional_t<avr::uart::has_usart<usart_digit>(), hardware_link<dev::clock>, software_link<dev::clock>>;
+#endif
 
-// The application's entry, an absolute address the linker pins (--defsym in
-// CMakeLists.txt): 0x0000 on the mega (word 0 stays the application's own
-// vector — BOOTRST re-vectors a reset into the loader in hardware) and the
-// trampoline word at base - 2 on the tinies. Reaching it must not depend on
-// where this copy runs, so the jump goes through a pointer: [[gnu::noipa]]
-// keeps the constant from folding back into a PC-relative call.
+// The application's entry, pinned by the linker (--defsym): word 0 on a
+// boot-sectioned mega, the trampoline at base − 2 elsewhere. Reaching it must
+// not depend on where this copy runs, so the jump goes through a pointer, and
+// [[gnu::noipa]] keeps the constant from folding back into a relative call.
 extern "C" [[noreturn]] void pureboot_app();
 
 [[gnu::noipa, noreturn]] void jump(void (*target)())
@@ -242,10 +198,8 @@ extern "C" [[noreturn]] void pureboot_app();
 	jump(pureboot_app);
 }
 
-// One activation window is a single 32-bit poll countdown. The divisor is
-// the backend's counted poll-loop cycles (its own comment reads them off the
-// compiled loop); whole-second precision is all the window promises, so the
-// nearest cycle count is plenty.
+// The window as one 32-bit countdown, divided by the backend's counted
+// poll-loop cycles. Whole seconds is all it promises.
 consteval std::uint32_t window_polls()
 {
 	return timeout_seconds * static_cast<std::uint32_t>(dev::clock.hz / link::poll_cycles);
@@ -261,8 +215,8 @@ bool pending_before_deadline()
 	return false;
 }
 
-// A knock byte under the activation deadline: an idle line means no host is
-// there, and the application runs.
+// A knock byte under the deadline: an idle window means no host, so the
+// application runs.
 std::uint8_t rx_deadline()
 {
 	if (!pending_before_deadline())
@@ -270,36 +224,61 @@ std::uint8_t rx_deadline()
 	return link::rx();
 }
 
-std::uint16_t rx16()
+// Inlined: read across a call, the first byte strands in a call-saved
+// register the caller has to push and pop.
+[[gnu::always_inline]] inline std::uint16_t rx16()
 {
 	std::uint16_t low = link::rx();
 	return static_cast<std::uint16_t>(low | (link::rx() << 8));
 }
 
-// The streamers take the count in the wire's 8-bit form: 0 means 256.
-// send_flash stays out of line: its two callers ('b' and 'R') otherwise each
-// inline a private copy of the loop. On the large chips the address is a
-// word address and the read goes through ELPM (flash_load_far).
-[[gnu::noinline]] void send_flash(std::uint16_t address, std::uint8_t count)
+// The wire's byte pair as the word it is — AVR is little-endian too, so the
+// cast is the identity a shift-and-or spelling makes the compiler rediscover.
+// Callers read into named variables first: the wire order is a sequence of
+// reads, not an argument order.
+[[gnu::always_inline]] inline std::uint16_t word_of(std::array<std::uint8_t, 2> pair)
+{
+	return std::bit_cast<std::uint16_t>(pair);
+}
+
+// Counts arrive in the wire's 8-bit form: 0 means 256. Both streamers fold
+// into the one command that reads flash, which is what lets the far one's
+// 24-bit cursor sit in the command loop's own call-saved registers.
+[[maybe_unused, gnu::always_inline]] inline void send_flash_near(std::uint16_t address, std::uint8_t count)
 {
-	if constexpr (word_flash) {
-		// The 24-bit cursor as the machine holds it: the RAMPZ byte and a
-		// 16-bit Z, carried explicitly (the reassembled 32-bit address
-		// folds away inside the inlined far load). A single read never
-		// crosses a 64 KiB boundary — the protocol forbids it and the host
-		// splits its chunks there — so RAMPZ holds for the whole run.
-		std::uint8_t rampz = static_cast<std::uint8_t>(address >> 15);
-		std::uint16_t z = static_cast<std::uint16_t>(address << 1);
-		do {
-			link::tx(avr::flash_load_far<std::uint8_t>((static_cast<std::uint32_t>(rampz) << 16) | z));
-			if (++z == 0)
-				++rampz; // robustness for a host that reads across 64 KiB
-		} while (--count);
-	} else {
 	do
 		link::tx(avr::flash_load(reinterpret_cast<const std::uint8_t *>(address++)));
 	while (--count);
 }
+
+// The 24-bit cursor as the machine holds it — the RAMPZ byte and a 16-bit Z,
+// carried apart; the reassembled address folds away inside the far load.
+[[maybe_unused, gnu::always_inline]] inline void send_flash_far(std::uint16_t address, std::uint8_t count)
+{
+	std::uint8_t rampz = static_cast<std::uint8_t>(address >> 15);
+	std::uint16_t z = static_cast<std::uint16_t>(address << 1);
+	do {
+		link::tx(avr::flash_load_far<std::uint8_t>((static_cast<std::uint32_t>(rampz) << 16) | z));
+		// Carrying the wrap is smaller than the flat 32-bit cursor GCC
+		// builds without it.
+		if (++z == 0)
+			++rampz;
+	} while (--count);
+}
+
+[[gnu::always_inline]] inline void send_flash(std::uint16_t address, std::uint8_t count)
+{
+	if constexpr (word_flash)
+		send_flash_far(address, count);
+	else
+		send_flash_near(address, count);
+}
+
+// Out of line: three sites send it, and a call is shorter than three
+// load-immediates.
+[[gnu::noinline]] void tx_ack()
+{
+	link::tx(ack);
 }
 
 void send_eeprom(std::uint16_t address, std::uint8_t count)
@@ -309,162 +288,157 @@ void send_eeprom(std::uint16_t address, std::uint8_t count)
 	while (--count);
 }
 
-// EEPROM write, host-paced: each ack goes out once the byte's write has
-// begun, so the next byte arrives while it completes and the following
-// write's own ready-wait sees an idle line. Nothing is ever missed, on
-// either serial backend, without a buffer.
+// Host-paced: the ack goes out once the write has begun, so the next byte
+// arrives while it completes and nothing is missed without a buffer.
 void store_eeprom(std::uint16_t address, std::uint8_t count)
 {
 	do {
 		ee::write<off>(address++, link::rx());
-		link::tx(ack);
+		tx_ack();
 	} while (--count);
 }
 
-// One flash page: stream the bytes into the SPM buffer as little-endian
-// words, then erase and program — except the 512-byte slot this code runs
-// in, which is drained but never programmed, so a copy can never erase
-// itself. `slot_high` is the high byte of that running slot's base (run()
-// derives it); a broken host thus cannot brick the running loader, and a
-// copy flashed one slot lower may rewrite the slot above it — how pureboot
-// updates itself. On the mega the RWW section is re-enabled so reads work
-// immediately.
+// One page into the SPM buffer, then erase and program — except the slot
+// this code is running in (`slot_high`, from run()), which is drained and
+// left alone. A broken host therefore cannot brick the running loader, and a
+// copy one slot lower may rewrite the resident one.
+//
+// Nothing discards the buffer first: it is write-once per word (§26.2.1), so
+// filling over a refused page or an application's leavings programs stale
+// words — but a page write auto-erases it (§26.2.1; §19.2 on the tinies), so
+// that write clears the condition and the host's read-back rewrites the page.
 void program_flash(std::uint16_t wire_address, std::uint8_t slot_high)
 {
-	// A buffer word cannot be loaded twice without an erase (§26.2.1), so a
-	// refused page's drained data must not linger for the next write:
-	// discard the buffer up front — CTPB on the tinies; on the megas
-	// writing RWWSRE aborts a pending load (§26.2.2 — on the m48s that
-	// flush is the bit's whole documented job).
-	if constexpr (rww_discard)
-		spm::rww_enable<off>();
-	else
-		spm::clear_buffer<off>();
-	// One induction either way. On the byte-addressed chips the wire address
-	// itself walks the page (aligned, so the offset bits wrap to zero); on
-	// the word-addressed large chips the wire word address becomes a 32-bit
-	// byte cursor once, and their 256-byte page makes its low byte the whole
-	// in-page offset. The slot index is one high byte of the wire address —
-	// two values on byte-addressed chips (the & ~1), bits 16:9 re-packed on
-	// the large ones.
+	// The address names a page, so its in-page bits are dropped and the walk
+	// starts at the page base — one induction either way: a byte-addressed
+	// wire address walks the page itself (the offset bits wrap back to zero),
+	// while a word one becomes a byte cursor once. The slot index is the wire
+	// address's high byte — on byte-addressed chips the byte address's, with
+	// the low bit dropped, since a slot is two of those.
 	spm::flash_address_t address;
 	std::uint8_t page_high;
 	if constexpr (word_flash) {
-		// Pages are aligned, so one page never crosses a 64 KiB boundary:
-		// RAMPZ is a per-page constant and the fill cursor is a 16-bit Z
-		// whose low byte is the whole in-page offset (256-byte pages). The
-		// slot index is simply the wire word address's high byte.
+		// A page is aligned, so it never crosses 64 KiB: RAMPZ is a per-page
+		// constant and the 16-bit Z's low byte is the whole in-page offset.
 		const std::uint8_t rampz = static_cast<std::uint8_t>(wire_address >> 15);
-		const std::uint16_t z0 = static_cast<std::uint16_t>(wire_address << 1);
+		const std::uint16_t z0 =
+		    static_cast<std::uint16_t>(wire_address << 1) & ~static_cast<std::uint16_t>(page - 1);
 		std::uint16_t z = z0;
 		do {
 			std::uint8_t low = link::rx();
 			std::uint8_t high = link::rx();
-			spm::fill<off>((static_cast<spm::flash_address_t>(rampz) << 16) | z,
-			               static_cast<std::uint16_t>(low | (high << 8)));
+			spm::fill<off>((static_cast<spm::flash_address_t>(rampz) << 16) | z, word_of({low, high}));
 			z += 2;
 		} while (static_cast<std::uint8_t>(z));
 		address = (static_cast<spm::flash_address_t>(rampz) << 16) | z0;
-		page_high = static_cast<std::uint8_t>(wire_address >> 8) & 0xfe;
+		page_high = static_cast<std::uint8_t>(wire_address >> 8);
 	} else {
-		address = static_cast<spm::flash_address_t>(wire_address);
+		address = static_cast<spm::flash_address_t>(wire_address & ~static_cast<std::uint16_t>(page - 1));
 		do {
 			std::uint8_t low = link::rx();
 			std::uint8_t high = link::rx();
-			spm::fill<off>(address, static_cast<std::uint16_t>(low | (high << 8)));
+			spm::fill<off>(address, word_of({low, high}));
 			address += 2;
 		} while (static_cast<std::uint8_t>(address) & (page - 1));
 		address -= 2; // back inside the page — erase and write ignore the word bits
 		page_high = static_cast<std::uint8_t>(address >> 8) & 0xfe;
 	}
 	if (page_high != slot_high) {
-		// The tinies and the m48s halt the CPU through the erase and the
-		// write, so only the boot-sectioned megas — running on while their
-		// RWW section programs — wait.
+		// Only a boot-sectioned mega runs on while its RWW section programs;
+		// everywhere else the CPU halts through erase and write.
 		spm::erase_page<off>(address);
 		if constexpr (boot_section)
 			spm::wait();
 		spm::write_page<off>(address);
-		if constexpr (boot_section) {
+		if constexpr (boot_section)
 			spm::wait();
+	}
+	// Programming leaves the RWW section disabled; reads need it back on. The
+	// same store discards the buffer (§26.2.2), so a boot-sectioned mega never
+	// meets the stale-word case above.
+	if constexpr (boot_section)
 		spm::rww_enable<off>();
 }
-	}
-}
 
-// The four fuse/lock bytes in the hardware's own Z order: low, lock,
-// extended, high. Writing fuses is not a thing self-programming can do on
-// AVR — SPM reaches flash (and boot lock bits) only.
+// The four fuse and lock bytes in the hardware's own Z order: low, lock,
+// extended, high.
 void send_fuses()
 {
 	std::uint8_t which = 0;
 	do
 		link::tx(spm::read_fuse<off>(static_cast<spm::fuse>(which)));
-	while (++which & 3);
+	while (++which != 4);
 }
 
 [[noreturn]] void run()
 {
-	// A watchdog reset belongs to the application (whose watchdog stays
-	// forced on until it clears WDRF) — no activation window in its way.
-	// The flag register is MCUSR, or the classic megas' MCUCSR.
+	// A watchdog reset belongs to the application, whose watchdog stays forced
+	// on until it clears WDRF — no activation window in its way.
 	if (avr::hw::field_impl<wdrf_field()>::test())
 		run_app();
 
 	link::init();
 
-	// The high byte of the 512-byte-aligned base this copy runs at: the
-	// return address is a word address, whose high byte is the 256-word slot
-	// index — on byte-addressed chips doubled back into byte terms.
-	// program_flash refuses this one slot and the info block is addressed
-	// from it, so both follow wherever the code was flashed.
+	// The high byte of the slot this copy runs at, which the write guard and
+	// the info block both follow: the return address is a word address, so its
+	// high byte is the 256-word slot index, doubled back into byte terms where
+	// the wire counts bytes. Taken as byteswap's low byte — the builtin already
+	// swaps the two stacked bytes, and the double swap folds away, where `>> 8`
+	// would leave the swap materialized.
 	const std::uint16_t ra_words = reinterpret_cast<std::uint16_t>(__builtin_return_address(0));
-	const std::uint8_t slot_high =
-	    word_flash ? static_cast<std::uint8_t>(ra_words >> 8) & 0xfe : static_cast<std::uint8_t>((ra_words >> 8) << 1);
+	const std::uint8_t ra_high = static_cast<std::uint8_t>(std::byteswap(ra_words));
+	const std::uint8_t slot_high = word_flash ? ra_high : static_cast<std::uint8_t>(ra_high << 1);
 
-	// The knock: 'p' then 'b', each under a fresh window; any other byte is
-	// line noise and waits again. Falling out of a window runs the app.
+	// 'p' then 'b', each under a fresh window; anything else is line noise.
 	while (rx_deadline() != 'p' || rx_deadline() != 'b') {
 	}
 
 	for (;;) {
-		// No prompt while an EEPROM write runs: a pending write blocks SPM
-		// and fuse reads (§26.2.1), and the ack tells the host all is done.
+		// No prompt while an EEPROM write runs: it blocks SPM and fuse reads
+		// (§26.2.1), and the prompt is the previous command's completion ack.
 		ee::wait();
-		link::tx(ack);
+		tx_ack();
 		const std::uint8_t command = link::rx();
 		switch (command) {
-		case 'b': { // info block, read relative to the running slot
-			// The block sits in the image's first 256 bytes (the build lint
-			// asserts it), and slots are 512-aligned — so the low byte of its
-			// link address (in wire units: bytes, or words on the large
-			// chips) is its offset in any slot, and the high byte of its
-			// runtime address is the running slot's. Built as a byte pair so
-			// no absolute address is ever materialized.
-			const auto link_low = reinterpret_cast<std::uint16_t>(info_data.data());
-			const std::uint8_t low =
-			    word_flash ? static_cast<std::uint8_t>(link_low >> 1) : static_cast<std::uint8_t>(link_low);
-			send_flash(std::bit_cast<std::uint16_t>(std::array{low, slot_high}),
-			           static_cast<std::uint8_t>(info_data.size()));
-			break;
-		}
 		case 'J': { // jump to a wire word address: hand-over and staging transfer
 			auto target = reinterpret_cast<void (*)()>(rx16());
-			link::tx(ack);
+			tx_ack();
 			link::drain();
 			jump(target);
 		}
+		case 'b':   // info block, read relative to the running slot
 		case 'R':   // read flash: addr16, n8 (0 = 256)
 		case 'r':   // read EEPROM: addr16, n8
 		case 'w': { // write EEPROM: addr16, n8, then n bytes each acked
-			std::uint16_t address = rx16();
-			std::uint8_t count = link::rx();
-			if (command == 'R')
-				send_flash(address, count);
-			else if (command == 'r')
+			// One address-and-count path for all four: 'b' is a flash read
+			// whose arguments the loader already knows, so it joins the
+			// wire-argument three rather than streaming from a call site of its
+			// own. That leaves one flash streamer in the image, and lets its
+			// cursor live in this never-returning loop's own call-saved
+			// registers instead of being saved and restored around a call.
+			std::uint16_t address;
+			std::uint8_t count;
+			if (command == 'b') {
+				// The block sits in the image's first 256 bytes (check_pi.py
+				// asserts it) and slots are 512-aligned, so the low byte of its
+				// link address is its offset in any slot — halved where wire
+				// units are words. The high byte is runtime data, so no
+				// absolute address is ever materialized.
+				const auto link_byte =
+				    static_cast<std::uint8_t>(reinterpret_cast<std::uint16_t>(info_data.storage.data()));
+				const std::uint8_t low = word_flash ? static_cast<std::uint8_t>(link_byte >> 1) : link_byte;
+				address = static_cast<std::uint16_t>(low | (slot_high << 8));
+				count = static_cast<std::uint8_t>(info_data.size());
+			} else {
+				address = rx16();
+				count = link::rx();
+			}
+			if (command == 'r')
 				send_eeprom(address, count);
-			else
+			else if (command == 'w')
 				store_eeprom(address, count);
+			else
+				send_flash(address, count);
 			break;
 		}
 		case 'W': // program one flash page: addr16, page bytes

pureboot/pureboot.py

@@ -1,24 +1,13 @@
 #!/usr/bin/env python3
-"""pureboot host tool — the smart half of the pureboot protocol (README.md).
+"""pureboot host tool — the smart half of the protocol (README.md).
 
-The device exposes primitives; this tool composes them: image loading (raw
-binary or Intel HEX), flash programming with read-back verification, erase as
-writing 0xff, EEPROM programming, fuse and info readout, the hand-over jump,
-and — on chips without a hardware boot section — the reset-vector surgery
-that re-homes the application's entry through the trampoline word below the
-loader. Page 0 and the trampoline are written first, so every interruption
-point of a flash leaves the chip reset-recoverable into the loader.
+The device exposes primitives; everything composite is here: HEX/raw images,
+programming with repairing read-back verification, the reset-vector surgery
+the boot-section-less chips need, and the self-update that stages the loader
+one slot lower and lets it rewrite the resident.
 
-It also updates the loader itself (--update-loader): pureboot's image is
-position-independent, so the tool installs the identical binary one 512-byte
-slot below the resident loader, jumps into that staging copy, lets it rewrite
-the resident slot, and restores what the staging slot held — resumable at
-every phase from the flash state plus a host-side state file carrying the
-saved bytes.
-
-Python standard library only; the serial port is driven with termios on POSIX
-and the Win32 serial API (through ctypes) on Windows, so any tty or COM port
-works — a USB adapter as well as a simavr pty.
+Standard library only. The port is termios on POSIX and the Win32 serial API
+through ctypes on Windows, so any tty or COM port works.
 """
 
 import argparse
@@ -35,14 +24,63 @@ else:
     import termios
 
 PROMPT = b"+"
-PROTOCOL_VERSION = 1
-SLOT = 512  # the loader slot on byte-addressed chips; word-addressed ones (>64 KiB) use 1 KiB — their own smallest boot sector
+VERSION = 2  # this tool's own version — free to drift from a loader's
+# The loader versions this tool speaks. A pureboot version implies its wire
+# protocol, which carries no number of its own, so this window is where that
+# map lives: every version so far speaks the same protocol, and one that
+# changes it becomes the new floor here.
+OLDEST_LOADER = 1
+NEWEST_LOADER = 3
+SLOT = 512  # the loader slot, on every chip
+RETRIES = 3  # rewrites of a page that reads back wrong, before the run stops
+
+VERBOSE = False
+
+
+def verbose(message):
+    if VERBOSE:
+        print(f"  {message}")
 
 
 class Error(Exception):
     pass
 
 
+class Progress:
+    """A transient bar on stderr, drawn only for a tty and erased when done —
+    logs and pipes see only the summary line each operation prints. No label
+    or a zero total disables it, so callers can pass one unconditionally."""
+
+    def __init__(self, label, total, unit="pages"):
+        self.label, self.total, self.unit = label, total, unit
+        self.done = 0
+        self.width = 0
+        self.live = bool(label) and total > 0 and sys.stderr.isatty()
+        self._draw()
+
+    def __enter__(self):
+        return self
+
+    def __exit__(self, *exc):
+        if self.live:
+            sys.stderr.write("\r" + " " * self.width + "\r")
+            sys.stderr.flush()
+
+    def step(self, n=1):
+        self.done += n
+        self._draw()
+
+    def _draw(self):
+        if not self.live:
+            return
+        bar = 24 * self.done // self.total
+        line = (f"{self.label:<16} [{'#' * bar}{'-' * (24 - bar)}] "
+                f"{100 * self.done // self.total:3d}% {self.done}/{self.total} {self.unit}")
+        self.width = max(self.width, len(line))
+        sys.stderr.write("\r" + line)
+        sys.stderr.flush()
+
+
 # ---------------------------------------------------------------- serial ---
 
 
@@ -266,24 +304,26 @@ class Info:
     def __init__(self, raw):
         if len(raw) != 12 or raw[0:2] != b"PB":
             raise Error(f"bad info block: {raw.hex()}")
-        if raw[2] != PROTOCOL_VERSION:
-            raise Error(f"protocol version {raw[2]}, tool speaks {PROTOCOL_VERSION}")
+        self.version = raw[2]
+        if not OLDEST_LOADER <= self.version <= NEWEST_LOADER:
+            raise Error(
+                f"pureboot {self.version}: this tool (version {VERSION}) speaks pureboot "
+                f"{OLDEST_LOADER}..{NEWEST_LOADER} — a newer loader needs a newer tool"
+            )
         self.raw = bytes(raw)
         self.signature = raw[3:6]
         self.page = raw[6] or 256  # the wire count convention: 0 means 256
         self.patch_vector = bool(raw[11] & 1)
-        # Large chips speak word addresses for flash (bit 1); the host keeps
-        # every address in bytes and converts at the wire.
+        # Bit 1: flash addresses are words on the wire. Every address here
+        # stays a byte address and converts at the wire.
         self.word_flash = bool(raw[11] & 2)
         scale = 2 if self.word_flash else 1
         self.base = (raw[7] | (raw[8] << 8)) * scale
         self.eeprom_size = raw[9] | (raw[10] << 8)
-        self.slot = 1024 if self.word_flash else SLOT
-        self.flash_size = self.base + self.slot
-        self.stage = self.base - self.slot  # where a staging copy of the loader goes
-        # The hand-over target, as the word address 'J' takes: the trampoline
-        # below the loader (tinies), or word 0 (mega — the application's own
-        # reset vector; BOOTRST re-vectors a reset into the loader instead).
+        self.flash_size = self.base + SLOT
+        self.stage = self.base - SLOT  # where a staging copy of the loader goes
+        # The hand-over target as 'J' takes it: the trampoline below the
+        # loader, or word 0 where BOOTRST re-vectors reset in hardware.
         self.app_entry_word = (self.base - 2) // 2 if self.patch_vector else 0
 
     def describe(self):
@@ -295,35 +335,66 @@ class Info:
             f"EEPROM {self.eeprom_size} B, {vector}"
         )
 
+    def lines(self):
+        """One fact per line — what --info prints."""
+        if self.patch_vector:
+            hand_over = f"host-patched reset vector, trampoline at {self.base - 2:#06x}"
+        else:
+            hand_over = "hardware boot section, jump to word 0"
+        return (
+            f"version      pureboot {self.version}",
+            f"signature    {' '.join(f'{b:02x}' for b in self.signature)}",
+            f"flash        {self.flash_size} B, {self.page} B pages"
+            + (", word-addressed wire" if self.word_flash else ""),
+            f"application  0x0000..{self.base - 1:#06x} ({self.base} B)",
+            f"loader       {self.base:#06x} ({SLOT} B slot)",
+            f"staging      {self.stage:#06x}",
+            f"EEPROM       {self.eeprom_size} B",
+            f"hand-over    {hand_over}",
+        )
+
 
 class Loader:
-    """A pureboot session. Between commands the loader has prompted `+` and
-    awaits a command byte; every method restores that invariant — except
-    jump(), after which the target must be knocked afresh."""
+    """A session. Between commands the loader has prompted and awaits a
+    command byte; every method restores that, except jump() — after which the
+    target must be knocked afresh."""
 
     def __init__(self, port):
         self.port = port
         self.info = None
 
     def connect(self, wait):
-        """Knock until the activation window answers, then read the info
-        block. Also converges when the loader already sits in its command
-        loop: the knock bytes are ignored-or-executed there, and the drain
-        absorbs whatever they produced."""
-        self.port.flush_input()
+        """Knock until the info block comes back. The block is what proves the
+        loader is listening — a prompt byte alone does not, since one left over
+        from a previous session can still be in the pipeline while the port
+        opening resets the device into a fresh activation window, where a
+        command without its knock is discarded. Each attempt is therefore the
+        whole handshake, retried until it produces the block or the window
+        closes. Also converges into a live session: the knock bytes are ignored
+        there and the drain absorbs whatever they produced."""
         deadline = time.monotonic() + wait
+        knocks = 0
         while True:
+            self.port.flush_input()
             self.port.write(b"pb")
+            knocks += 1
             if PROMPT in self.port.read_available(0.4):
-                break
-            if time.monotonic() > deadline:
-                raise Error("no answer — reset the device within its activation window")
                 while self.port.read_available(0.3):
                     pass
                 self.port.write(b"b")
-        self.info = Info(self.port.read_exact(12, 2.0))
+                try:
+                    block = self.port.read_exact(12, 2.0)
+                except Error:
+                    block = b""
+                # A version the tool cannot speak is the loader's own answer,
+                # not a failed knock: Info reports it rather than retrying.
+                if block[0:2] == b"PB":
+                    self.info = Info(block)
                     self._expect_prompt()
+                    verbose(f"loader answered knock {knocks}; info block read")
                     return self.info
+            if time.monotonic() > deadline:
+                raise Error("no answer — reset the device within its activation window")
 
     def _expect_prompt(self, timeout=2.0):
         byte = self.port.read_exact(1, timeout)
@@ -373,7 +444,7 @@ class Loader:
         head = bytes((ord("W"), wire & 0xFF, wire >> 8))
         self._command(head + data, 0, 2.0)
 
-    def write_eeprom(self, address, data):
+    def write_eeprom(self, address, data, progress=None):
         offset = 0
         while offset < len(data):
             chunk = data[offset : offset + 256]
@@ -382,6 +453,8 @@ class Loader:
             for byte in chunk:
                 self.port.write(bytes((byte,)))
                 self._expect_prompt()  # per-byte ack: the write has begun
+                if progress:
+                    progress.step()
             self._expect_prompt()  # the next command prompt
             address += len(chunk)
             offset += len(chunk)
@@ -390,16 +463,13 @@ class Loader:
         return self._command(b"F", 4, 2.0)
 
     def jump(self, word_address):
-        """'J': the device acks, then execution continues at the word
-        address — a loader slot's base (whose copy must then be knocked
-        afresh) or the application entry."""
+        """The device acks, then execution continues at the word address."""
         self.port.write(bytes((ord("J"), word_address & 0xFF, word_address >> 8)))
         self._expect_prompt()
 
     def enter_copy(self, byte_address, wait):
-        """Jump into the loader copy at `byte_address` and knock it. Ending
-        up in the copy addressed is guaranteed by construction: a jump to a
-        slot base lands in that slot's entry stub."""
+        """Jump into the loader copy at `byte_address` and knock it — a slot
+        base is that copy's entry stub, so it can only land there."""
         self.jump(byte_address // 2)
         return self.connect(wait)
 
@@ -487,21 +557,22 @@ def plan_flash(image, info):
             final += bytearray([0xFF] * (trampoline_page + page - len(final)))
         jump = rjmp_to(trampoline_word, entry, flash_words)
         final[info.base - 2], final[info.base - 1] = jump & 0xFF, jump >> 8
+        verbose(f"vector surgery: word 0 -> loader {info.base:#06x}, "
+                f"trampoline {info.base - 2:#06x} -> entry word {entry:#06x}")
 
     pages = {a: bytes(final[a : a + page]) for a in range(0, len(final), page)}
     return pages
 
 
 def covered(pages, info, skip_blank):
-    """Pages in programming order; optionally dropping all-0xff pages (sound
-    only over erased flash) — never a load-bearing one.
+    """Pages in programming order, optionally dropping all-0xff ones (sound
+    only over erased flash, and never a load-bearing page).
 
-    With a patched vector (tinies), the patched page 0 goes first and the
-    trampoline page second: from the first write on, a reset lands in the
-    loader and the loader's own fall-through lands on the application entry,
-    so every interruption point of the flash is recoverable. With a hardware
-    boot section a reset re-vectors to the loader regardless; ascending
-    order, page 0 last, maximizes what an interrupted image retains."""
+    A patched vector puts page 0 first and the trampoline page second, so from
+    the first write on a reset lands in the loader and its fall-through on the
+    application entry — every interruption point recoverable. A hardware boot
+    section re-vectors reset regardless; page 0 goes last there, which
+    maximizes what an interrupted image retains."""
     trampoline_page = info.base - info.page if info.patch_vector else None
     first = [0, trampoline_page] if info.patch_vector else []
     rest = [a for a in sorted(pages) if a not in first]
@@ -567,18 +638,21 @@ def mega_boot(info, fuse_bytes):
 
 
 def image_info(image):
-    """The info block embedded in a pureboot binary, or None."""
-    at = image.find(b"PB" + bytes((PROTOCOL_VERSION,)))
-    return Info(image[at : at + 12]) if 0 <= at <= len(image) - 12 else None
+    """The info block embedded in a pureboot binary, or None. Searched once
+    per known version, so the magic stays three selective bytes rather than
+    two that code could carry by chance."""
+    for version in range(OLDEST_LOADER, NEWEST_LOADER + 1):
+        at = image.find(b"PB" + bytes((version,)))
+        if 0 <= at <= len(image) - 12:
+            return Info(image[at : at + 12])
+    return None
 
 
 def loader_image(path):
-    """A loader update image, as the slot's own content. A raw binary is that
-    already; an Intel HEX links the loader at its base inside an otherwise
-    blank flash image, and load_image() anchors every image at zero, so the
-    blank below the base is dropped here. The base comes from the image's own
-    info block rather than the device's, so an image built for somewhere else
-    survives intact and the preflight can say so."""
+    """An update image as the slot's own content: a raw binary already is,
+    while a HEX carries the blank below the loader's base, which is peeled off
+    here. The base comes from the image's own block, not the device's, so a
+    foreign image survives intact for the preflight to reject by name."""
     image = load_image(path)
     embedded = image_info(image)
     if embedded and len(image) > embedded.base:
@@ -587,18 +661,17 @@ def loader_image(path):
 
 
 def staging_content(image, info):
-    """The 512-byte staging-slot content: the image, padding, and — on
-    chips whose hand-over jumps through the word below the resident loader —
-    that word, which for a staging copy is the slot's own last word: an rjmp
-    to the resident base. The staging copy's fall-through and 'J'-free exit
-    both land in a loader instead of garbage."""
-    slot = info.slot
-    if len(image) > (slot - 2 if info.patch_vector else slot):
-        raise Error(f"loader image is {len(image)} B, the slot holds {slot - 2 if info.patch_vector else slot}")
-    content = bytearray(image) + bytearray([0xFF] * (slot - len(image)))
+    """The staging slot's content: the image, padding, and — where the
+    hand-over jumps through the word below the resident — that word, which for
+    a staging copy is its own last one. Composed as an rjmp to the resident,
+    so an abandoned staging copy still falls through into a loader."""
+    budget = SLOT - 2 if info.patch_vector else SLOT
+    if len(image) > budget:
+        raise Error(f"loader image is {len(image)} B, the slot holds {budget}")
+    content = bytearray(image) + bytearray([0xFF] * (SLOT - len(image)))
     if info.patch_vector:
         through = rjmp_to((info.base - 2) // 2, info.base // 2, info.flash_size // 2)
-        content[slot - 2], content[slot - 1] = through & 0xFF, through >> 8
+        content[SLOT - 2], content[SLOT - 1] = through & 0xFF, through >> 8
     return bytes(content)
 
 
@@ -606,7 +679,10 @@ def update_preflight(image, info, fuse_bytes):
     """Errors and warnings before any flash is touched. Returns warnings."""
     embedded = image_info(image)
     if embedded is None:
-        raise Error("no pureboot info block in the update image — not a pureboot binary?")
+        raise Error(
+            "no pureboot info block in the update image — not a pureboot binary, "
+            f"or a version this tool ({VERSION}) does not know"
+        )
     if embedded.raw[3:] != info.raw[3:]:
         raise Error(
             f"update image is for another target: it declares "
@@ -621,7 +697,7 @@ def update_preflight(image, info, fuse_bytes):
             raise Error(
                 f"cannot self-update: the staging slot {info.stage:#06x} lies below the "
                 f"boot section ({bls_start:#06x}) where SPM is disabled "
-                f"— a boot section of at least two slots ({2 * info.slot} B, BOOTSZ) is "
+                f"— a boot section of at least two slots ({2 * SLOT} B, BOOTSZ) is "
                 f"required, and only an external programmer can change fuses"
             )
         if not bootrst:
@@ -663,7 +739,7 @@ class UpdateState:
         self.data = {
             "signature": info.signature.hex(),
             "base": info.base,
-            "staging": loader.read_flash(info.stage, info.slot).hex(),
+            "staging": loader.read_flash(info.stage, SLOT).hex(),
             "page0": loader.read_flash(0, info.page).hex() if info.patch_vector else "",
         }
         with open(self.path, "w") as f:
@@ -681,26 +757,46 @@ class UpdateState:
         os.unlink(self.path)
 
 
-def write_differing(loader, base, content, order=None):
-    """Program the pages of `content` at `base` that differ from flash —
-    idempotent, so a resumed phase redoes only what an interruption left."""
+def write_differing(loader, base, content, order=None, label=None):
+    """Program the pages of `content` at `base` that differ from flash, so a
+    resumed phase redoes only what an interruption left."""
     page = loader.info.page
-    offsets = order if order is not None else range(0, len(content), page)
+    offsets = list(order) if order is not None else list(range(0, len(content), page))
     written = 0
+    with Progress(label, len(offsets)) as bar:
         for offset in offsets:
             want = content[offset : offset + page]
             if loader.read_flash(base + offset, page) != want:
                 loader.write_page(base + offset, want)
                 written += 1
-    for at in range(0, len(content), 256):
-        if loader.read_flash(base + at, min(256, len(content) - at)) != content[at : at + 256]:
-            raise Error(f"verify failed at {base + at:#06x} after programming")
+            bar.step()
+    if label:
+        verbose(f"{label}: {written} of {len(offsets)} pages differed")
+    # The same bounded repair as verify_pages: here a page left wrong is a
+    # half-written loader slot.
+    for retry in range(RETRIES + 1):
+        bad = [
+            offset
+            for offset in range(0, len(content), page)
+            if loader.read_flash(base + offset, len(content[offset : offset + page])) != content[offset : offset + page]
+        ]
+        if not bad:
+            break
+        if retry == RETRIES:
+            raise Error(
+                f"verify failed at {base + bad[0]:#06x} after programming "
+                f"(still wrong after {RETRIES} retries)"
+            )
+        for offset in bad:
+            verbose(f"rewriting page {base + offset:#06x} (retry {retry + 1})")
+            loader.write_page(base + offset, content[offset : offset + page])
+            written += 1
     return written
 
 
 def patch_word0(loader, page0, target_base):
-    """Rewrite page 0 with its word 0 re-aimed at `target_base` — the
-    resume insurance around rewriting a loader slot the reset path uses."""
+    """Re-aim word 0 at `target_base` — the resume insurance around
+    rewriting a loader slot the reset path goes through."""
     info = loader.info
     patched = bytearray(page0)
     word = rjmp_to(0, target_base // 2, info.flash_size // 2)
@@ -710,80 +806,79 @@ def patch_word0(loader, page0, target_base):
 
 
 def op_update_loader(loader, wait, path, state_path, fuse_bytes):
-    """Replace the resident loader with `path`, using the loader itself as
-    its own staging loader. Every phase is idempotent and keyed off the
-    actual flash state, so a re-run after any interruption resumes; the
-    state file carries the bytes the staging slot held."""
+    """Replace the resident loader with `path`, using the loader as its own
+    staging loader. Every phase is idempotent and keyed off the flash state,
+    so a re-run resumes; the state file carries what the staging slot held."""
     info = loader.info
     image = loader_image(path)
     for warning in update_preflight(image, info, fuse_bytes):
         print(f"note: {warning}")
+    update = image_info(image)  # the preflight proved it is there
+    verbose(f"installing pureboot {update.version} over pureboot {info.version}")
     staged = staging_content(image, info)
-    resident = bytes(image) + bytes([0xFF] * (info.slot - len(image)))
+    resident = bytes(image) + bytes([0xFF] * (SLOT - len(image)))
     page = info.page
 
     state = UpdateState(state_path)
+    if os.path.exists(state_path):
+        verbose(f"resuming the update recorded in {state_path}")
+    else:
+        verbose(f"saving the staging slot to {state_path}")
     state.load_or_save(loader)
 
-    # Install the staging copy — unless a loader already sits whole in the
-    # staging slot (a build programmed there by hand): that copy IS the
-    # installed staging copy, and rewriting it would only trip its own
-    # running-slot guard on the composed through-word. Any pureboot with
-    # the device's own info block serves — the staged copy just streams
-    # pages, so an older build installs a newer resident all the same. Two
-    # checks make "already a loader" mean a *complete* one: the block must
-    # sit where every image carries it (within the slot's first 256 bytes
-    # — the build's position lint), matching the device's block byte for
-    # byte, and the slot must be unchanged since this update began (the
-    # state file's snapshot) — a resumed, half-written install differs
-    # from its snapshot and takes the install path below, which completes
-    # it page by page.
-    current = loader.read_flash(info.stage, info.slot)
+    # A loader already sitting whole in the staging slot IS the staging copy:
+    # rewriting it would only meet its own running-slot guard. Any pureboot
+    # with the device's info block serves, since a staged copy only streams
+    # pages. "Whole" needs both checks — the block where every image carries
+    # it and matching byte for byte, and the slot unchanged since this update
+    # began, so a half-written install takes the path below instead.
+    current = loader.read_flash(info.stage, SLOT)
     staged_loader = image_info(current[:268])
     if staged_loader is not None and staged_loader.raw == info.raw and current == state.staging:
-        print(f"staging slot already holds a loader — left in place")
+        print("staging slot already holds a loader — left in place")
     else:
-        # On a chip whose staging slot starts at address 0 (the 1 KB
-        # tiny13s), its first page carries the reset vector: written last,
-        # so any earlier interruption still resets into the old resident,
-        # and from then on resets enter the staging copy.
-        order = list(range(0, info.slot, page))
+        # Where the staging slot starts at address 0 (the 1 KB tiny13s) its
+        # first page carries the reset vector, so it goes last: until then a
+        # reset still reaches the old resident.
+        order = list(range(0, SLOT, page))
         if info.stage == 0:
             order = order[1:] + [0]
-        if write_differing(loader, info.stage, staged, order):
+        if write_differing(loader, info.stage, staged, order, label="staging copy"):
             print(f"staging copy installed at {info.stage:#06x}")
 
-    # Enter it and let it rewrite the resident slot. Where a patched reset
-    # vector routes through the resident (a tiny with the staging slot away
-    # from page 0), word 0 is re-aimed at the staging copy around the
-    # rewrite, so a power failure mid-rewrite still resets into a loader.
+    # Enter it and let it rewrite the resident. Where a patched reset vector
+    # routes through the resident, word 0 is re-aimed at the staging copy for
+    # the rewrite, so a power loss mid-rewrite still resets into a loader.
+    verbose(f"entering the staging copy at {info.stage:#06x}")
     loader.enter_copy(info.stage, wait)
     redirect = info.patch_vector and info.stage != 0
     if redirect:
+        verbose("word 0 re-aimed at the staging copy for the rewrite")
         patch_word0(loader, state.page0, info.stage)
-    if write_differing(loader, info.base, resident):
+    if write_differing(loader, info.base, resident, label="resident"):
         print(f"resident loader rewritten at {info.base:#06x}")
 
     # Enter the new resident and put the staging region back: page 0 first
     # where it lives in that region (word 0 then points at the new resident
     # for the rest of the restore), the saved trampoline with the rest.
+    verbose(f"entering the new resident at {info.base:#06x}")
     loader.enter_copy(info.base, wait)
     if redirect:
+        verbose("word 0 restored")
         write_differing(loader, 0, state.page0)
-    order = list(range(0, info.slot, page))
+    order = list(range(0, SLOT, page))
     if info.stage == 0:
         order = [0] + order[1:]
-    write_differing(loader, info.stage, state.staging, order)
+    write_differing(loader, info.stage, state.staging, order, label="staging restore")
 
     state.discard()
-    print(f"loader updated: {len(image)} B at {info.base:#06x}, staging region restored")
+    print(f"loader updated: pureboot {update.version}, {len(image)} B at {info.base:#06x}, staging region restored")
 
 
 def check_walk_region(pages, info, fuse_bytes, force):
-    """With BOOTRST programmed but targeting below the loader, reset reaches
-    the loader only by walking across erased flash from the boot-section
-    start; application data in that span would divert reset into itself.
-    Only checkable when the fuses are known (--fuses or --assume-fuses)."""
+    """BOOTRST programmed below the loader means reset reaches it only by
+    walking across erased flash; application data in that span would divert
+    reset into itself. Needs the fuses (--fuses or --assume-fuses)."""
     if info.patch_vector or fuse_bytes is None:
         return
     bootrst, bls_start = mega_boot(info, fuse_bytes)
@@ -802,54 +897,89 @@ def check_walk_region(pages, info, fuse_bytes, force):
 
 
 def op_erase_flash(loader):
-    """0xff over the whole application area. Descending on a patched-vector
-    chip: page 0 — the patched reset vector — goes last, so an interrupted
-    erase still resets into the loader, and once it is gone the whole area
-    is erased and the reset walk reaches the loader anyway."""
+    """0xff over the application area, descending where the reset vector is
+    patched: page 0 goes last, so an interrupted erase still resets into the
+    loader — and once it is gone, the erased walk reaches it anyway."""
     blank = bytes([0xFF] * loader.info.page)
     addresses = range(0, loader.info.base, loader.info.page)
+    with Progress("erase", len(addresses)) as bar:
         for address in reversed(addresses) if loader.info.patch_vector else addresses:
             loader.write_page(address, blank)
+            bar.step()
     print(f"erase: {loader.info.base // loader.info.page} pages")
 
 
 def op_erase_eeprom(loader):
-    loader.write_eeprom(0, bytes([0xFF] * loader.info.eeprom_size))
+    with Progress("erase EEPROM", loader.info.eeprom_size, "B") as bar:
+        loader.write_eeprom(0, bytes([0xFF] * loader.info.eeprom_size), progress=bar)
     print(f"erase: {loader.info.eeprom_size} B of EEPROM")
 
 
 def op_flash(loader, path, erase, verify, fuse_bytes=None, force=False):
     image = load_image(path)
+    verbose(f"{path}: {len(image)} B image")
     pages = plan_flash(image, loader.info)
     check_walk_region(pages, loader.info, fuse_bytes, force)
     if erase:
         op_erase_flash(loader)
     order = covered(pages, loader.info, skip_blank=erase)
+    if len(order) != len(pages):
+        verbose(f"{len(pages) - len(order)} blank pages skipped (erased flash underneath)")
+    with Progress("flash", len(order)) as bar:
         for address in order:
             loader.write_page(address, pages[address])
+            bar.step()
     print(f"flash: {path}: {len(order)} pages")
     if verify:
-        verify_pages(loader, pages)
+        verify_pages(loader, pages, repair=True)
 
 
-def verify_pages(loader, pages):
+def verify_pages(loader, pages, repair=False):
+    """Read every page back and compare. With `repair`, a mismatch is
+    rewritten and re-read up to RETRIES times first: a page filled over a
+    dirty SPM buffer takes stale words, and the write that took them cleared
+    the buffer, so one rewrite settles it. Anything still wrong is not that."""
+    repaired = 0
+    with Progress("verify", len(pages)) as bar:
         for address in sorted(pages):
+            for retry in range(RETRIES + 1):
                 got = loader.read_flash(address, loader.info.page)
-        if got != pages[address]:
+                if got == pages[address]:
+                    break
                 first = next(i for i in range(len(got)) if got[i] != pages[address][i])
-            raise Error(
+                detail = (
                     f"verify failed at {address + first:#06x}: "
                     f"wrote {pages[address][first]:02x}, read {got[first]:02x}"
                 )
-    print(f"verify: {len(pages)} pages ok")
+                if not repair:
+                    raise Error(detail)
+                if retry == RETRIES:
+                    raise Error(f"{detail} (still wrong after {RETRIES} retries)")
+                verbose(f"{detail} — rewriting page {address:#06x} (retry {retry + 1})")
+                loader.write_page(address, pages[address])
+                repaired += 1
+            bar.step()
+    note = f", {repaired} page rewrite(s)" if repaired else ""
+    print(f"verify: {len(pages)} pages ok{note}")
 
 
 def op_verify_flash(loader, path):
     verify_pages(loader, plan_flash(load_image(path), loader.info))
 
 
+def read_progress(reader, total, label):
+    """A bulk read in 256-byte wire chunks under a progress bar."""
+    data = b""
+    with Progress(label, total, "B") as bar:
+        while len(data) < total:
+            chunk = min(256, total - len(data))
+            data += reader(len(data), chunk)
+            bar.step(chunk)
+    return data
+
+
 def op_read_flash(loader, path):
-    data = loader.read_flash(0, loader.info.base)
+    data = read_progress(loader.read_flash, loader.info.base, "read flash")
     open(path, "wb").write(data)
     print(f"read flash: {len(data)} B -> {path}")
 
@@ -860,10 +990,11 @@ def op_eeprom(loader, path, erase, verify):
         raise Error(f"EEPROM image is {len(image)} B, device has {loader.info.eeprom_size}")
     if erase:
         op_erase_eeprom(loader)
-    loader.write_eeprom(0, image)
+    with Progress("eeprom", len(image), "B") as bar:
+        loader.write_eeprom(0, image, progress=bar)
     print(f"eeprom: {path}: {len(image)} B")
     if verify:
-        got = loader.read_eeprom(0, len(image))
+        got = read_progress(loader.read_eeprom, len(image), "verify EEPROM")
         if got != image:
             first = next(i for i in range(len(got)) if got[i] != image[i])
             raise Error(f"verify failed at EEPROM {first:#06x}: wrote {image[first]:02x}, read {got[first]:02x}")
@@ -872,7 +1003,7 @@ def op_eeprom(loader, path, erase, verify):
 
 def op_verify_eeprom(loader, path):
     image = load_image(path)
-    got = loader.read_eeprom(0, len(image))
+    got = read_progress(loader.read_eeprom, len(image), "verify EEPROM")
     if got != image:
         first = next(i for i in range(len(got)) if got[i] != image[i])
         raise Error(f"verify failed at EEPROM {first:#06x}: expected {image[first]:02x}, read {got[first]:02x}")
@@ -880,15 +1011,30 @@ def op_verify_eeprom(loader, path):
 
 
 def op_read_eeprom(loader, path):
-    data = loader.read_eeprom(0, loader.info.eeprom_size)
+    data = read_progress(loader.read_eeprom, loader.info.eeprom_size, "read EEPROM")
     open(path, "wb").write(data)
     print(f"read EEPROM: {len(data)} B -> {path}")
 
 
 def op_fuses(loader):
     low, lock, extended, high = loader.read_fuses()
-    print(f"fuses: low {low:02x} high {high:02x} extended {extended:02x} lock {lock:02x}")
-    return bytes((low, lock, extended, high))
+    print("fuses:")
+    print(f"  low       0x{low:02x}")
+    print(f"  high      0x{high:02x}")
+    print(f"  extended  0x{extended:02x}")
+    print(f"  lock      0x{lock:02x}")
+    fuse_bytes = bytes((low, lock, extended, high))
+    # On a boot-sectioned mega the BOOTSZ/BOOTRST decode is the fuse fact the
+    # loader's whole deployment hangs on — say it in words.
+    if not loader.info.patch_vector:
+        try:
+            bootrst, bls_start = mega_boot(loader.info, fuse_bytes)
+            reset = "reset enters it" if bootrst else "reset boots the application"
+            print(f"  boot      section at {bls_start:#06x} ({loader.info.flash_size - bls_start} B), "
+                  f"BOOTRST {'programmed' if bootrst else 'unprogrammed'} — {reset}")
+        except Error:
+            pass  # unknown signature: the raw bytes above still stand
+    return fuse_bytes
 
 
 # -------------------------------------------------------------------- cli ---
@@ -898,6 +1044,8 @@ def main():
     parser = argparse.ArgumentParser(
         description="pureboot host tool", epilog="operations run in the order listed above"
     )
+    parser.add_argument("--version", action="version", version=f"%(prog)s {VERSION} "
+                        f"(speaks pureboot {OLDEST_LOADER}..{NEWEST_LOADER})")
     parser.add_argument("--port", required=True, help="serial device: COM6, /dev/ttyUSB0, or a simavr pty")
     parser.add_argument("--baud", type=int, default=115200, help="115200 mega, 57600 tinies")
     parser.add_argument("--wait", type=float, default=30.0, help="seconds to keep knocking")
@@ -918,7 +1066,11 @@ def main():
     parser.add_argument("--verify-eeprom", metavar="FILE", help="compare EEPROM against an image")
     parser.add_argument("--force", action="store_true", help="override refusable safety checks")
     parser.add_argument("--stay", action="store_true", help="leave the loader in its session")
+    parser.add_argument("-v", "--verbose", action="store_true",
+                        help="print decisions and derived facts as operations run")
     args = parser.parse_args()
+    global VERBOSE
+    VERBOSE = args.verbose
 
     if args.update_loader and (args.flash or args.erase_flash):
         parser.error("--update-loader does not combine with application flash operations")
@@ -931,11 +1083,14 @@ def main():
             parser.error("--assume-fuses takes 8 hex digits: low,lock,extended,high")
 
     port = Port(args.port, args.baud)
+    verbose(f"{args.port}: {args.baud} Bd 8N1, DTR/RTS asserted")
     try:
         loader = Loader(port)
         info = loader.connect(args.wait)
         if args.info:
-            print(f"device: {info.describe()}")
+            print("device:")
+            for line in info.lines():
+                print(f"  {line}")
         fuse_bytes = fuse_override
         if args.fuses or (args.update_loader and not info.patch_vector and fuse_bytes is None):
             read = op_fuses(loader)

test/check_pi.py

@@ -1,17 +1,11 @@
 #!/usr/bin/env python3
-"""Position-independence lint for the pureboot image.
+"""Position-independence lint: the two link-time facts that let the identical
+image run from any slot, asserted from the built ELF.
 
-The self-staging design lets the identical binary run from any 512-byte
-slot, which holds only if nothing in the image addresses itself absolutely.
-Two link-time facts guarantee it, both asserted here from the built ELF:
-
-  1. No absolute jmp/call opcodes — all control flow is PC-relative
-     (rjmp/rcall/ijmp/icall). -mrelax normally guarantees this; a code
-     change that grows a branch out of relaxation range would break it
-     silently.
-  2. The info block sits within the image's first 256 bytes: the 'b'
-     command rebuilds its address as (running slot high byte : low byte of
-     the link address), which needs the offset to fit that low byte.
+  1. No absolute jmp/call — -mrelax normally guarantees it, but a branch that
+     grows out of relaxation range would break it silently.
+  2. The info block within the image's first 256 bytes: 'b' rebuilds its
+     address as (running slot high byte : link address low byte).
 
 Usage: check_pi.py <objdump> <nm> <elf> <text_start_hex>
 """
@@ -37,11 +31,12 @@ def main():
         sys.exit(1)
 
     symbols = subprocess.run([nm, "-C", elf], capture_output=True, text=True, check=True).stdout
-    info = [line for line in symbols.splitlines() if "info_data" in line]
+    info = [line for line in symbols.splitlines() if "flash_table" in line and "::storage" in line]
     if len(info) != 1:
         print(f"FAIL: expected one info-block storage symbol, found {len(info)}")
         sys.exit(1)
-    offset = int(info[0].split()[0], 16) - text_start
+    address = int(info[0].split()[0], 16)
+    offset = address - text_start
     if not 0 <= offset < 256:
         print(f"FAIL: info block at image offset {offset:#x}, must sit in the first 256 bytes")
         sys.exit(1)

test/pbapp.cpp

@@ -4,11 +4,16 @@
 // surgery, actually launched it. Linked normally (crt, vectors at 0); on
 // the tinies its reset vector is the rjmp the host re-homes.
 //
-// On the mega it then listens, and an 'L' makes it jump into the resident
-// loader — the application-owned loader entry a BOOTRST-unprogrammed mega
-// relies on (reset always boots the application there), exercised by the
-// self-update tests. The tinies idle: reset reaches their loader through
-// the patched vector, so the application owes it nothing.
+// On the hardware-USART link it then listens, and an 'L' makes it jump into
+// the resident loader — the application-owned loader entry a
+// BOOTRST-unprogrammed mega relies on (reset always boots the application
+// there), exercised by the self-update tests. The software link idles:
+// reset reaches those loaders through the patched vector (or the runner
+// models BOOTRST), so the application owes them nothing.
+//
+// The fixture speaks the deployment its loader was built for: the same
+// PUREBOOT_* defines configure it, and without them it assumes the stock
+// deployment (the crystal/RC clock table below, the chip's natural link).
 #include <libavr/libavr.hpp>
 
 using namespace avr::literals;
@@ -17,37 +22,77 @@ namespace {
 
 consteval avr::hertz_t clock()
 {
+#if defined(PUREBOOT_CLOCK_HZ)
+	return avr::hertz_t{PUREBOOT_CLOCK_HZ};
+#else
 	auto name = std::string_view{avr::hw::db.name};
 	if (name.starts_with("ATtiny13"))
 		return 9.6_MHz;
 	if (name.starts_with("ATtiny"))
 		return 8_MHz;
 	return 16_MHz;
+#endif
+}
+
+#if !defined(PUREBOOT_TX)
+#define PUREBOOT_TX pb1
+#endif
+#if !defined(PUREBOOT_USART)
+#define PUREBOOT_USART 0
+#endif
+
+consteval bool use_hardware()
+{
+#if defined(PUREBOOT_SOFT_SERIAL)
+	return false;
+#else
+	return avr::hw::db.has_instance("USART0") || avr::hw::db.has_instance("USART");
+#endif
 }
 
 using dev = avr::device<{.clock = clock()}>;
 
-template <avr::hertz_t C, bool Hardware = avr::hw::db.has_instance("USART0") || avr::hw::db.has_instance("USART")>
+template <avr::hertz_t C, bool Hardware = use_hardware()>
 struct link {
-	using tx_t = avr::uart::usart0<C, {.baud = 115200_Bd, .max_baud_error = 2.5_pct}>;
+#if defined(PUREBOOT_BAUD)
+	static constexpr avr::baud_t baud{PUREBOOT_BAUD};
+#else
+	static constexpr avr::baud_t baud{115200};
+#endif
+	using tx_t = avr::uart::usart<'0' + PUREBOOT_USART, C, {.baud = baud, .max_baud_error = 2.5_pct}>;
 	static void tx(char c)
 	{
 		tx_t::write(static_cast<std::uint8_t>(c));
 	}
 	[[noreturn]] static void idle()
 	{
-		// 'L' hands back to the loader at the top slot — 512 bytes, or the
-		// 1 KiB the >64 KiB chips use.
-		constexpr std::uint32_t slot = avr::hw::db.mem.flash_size > 65536 ? 1024 : 512;
-		for (;;)
-			if (tx_t::read_blocking() == 'L')
+		// 'L' hands back to the loader in the top slot — 512 bytes on every
+		// chip. The jump takes a word address, which is what makes the
+		// >64 KiB chips' entry reachable through a 16-bit pointer at all.
+		constexpr std::uint32_t slot = 512;
+		for (;;) {
+			auto command = tx_t::read_blocking();
+			if (command == 'L')
 				reinterpret_cast<void (*)()>(static_cast<std::uint16_t>((avr::hw::db.mem.flash_size - slot) / 2))();
+			// 'D' leaves every word of the SPM page buffer dirty, so that a
+			// following 'L' enters the loader with the buffer it never clears.
+			if (command == 'D') {
+				for (std::uint16_t at = 0; at < avr::spm::page_bytes; at += 2)
+					avr::spm::fill(at, 0xdead);
+				tx('D');
+			}
+		}
 	}
 };
 
 template <avr::hertz_t C>
 struct link<C, false> {
-	using tx_t = avr::uart::software_tx<C, avr::pb1, 57600_Bd>;
+#if defined(PUREBOOT_BAUD)
+	static constexpr avr::baud_t baud{PUREBOOT_BAUD};
+#else
+	static constexpr avr::baud_t baud{57600};
+#endif
+	using tx_t = avr::uart::software_tx<C, avr::PUREBOOT_TX, baud>;
 	static void tx(char c)
 	{
 		tx_t::write(static_cast<std::uint8_t>(c));

test/pbdirty.py

@@ -0,0 +1,88 @@
+#!/usr/bin/env python3
+"""Dirty-page-buffer acceptance test: with no discard in the loader, a page
+filled over words an earlier writer left takes those instead. The whole
+contract is asserted — a bare verify sees the corruption, the repairing
+verify fixes it in one rewrite, and it stays fixed.
+
+The state is reached the one way the loader cannot prevent: an application
+dirties the buffer and jumps in with no reset between. Boot-sectioned megas
+forbid that outright (SPM runs only from the boot section, Atmel-8271 §26.2),
+but simavr dispatches SPM from anywhere, which is what makes it constructible.
+
+Usage: pbdirty.py <device_bin> <pureboot_elf> <mcu> <hz> <base_hex> <page>
+                  <baud> <app_bin> <tool_py> <workdir>
+"""
+
+import os
+import sys
+
+
+def fail(message):
+    print(f"FAIL: {message}")
+    sys.exit(1)
+
+
+def main():
+    device_bin, elf, mcu, hz, base_hex, page, baud, app_bin, tool, workdir = sys.argv[1:]
+    page, baud = int(page), int(baud)
+    sys.path.insert(0, os.path.dirname(os.path.abspath(tool)))
+    sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
+    import pbsim
+    import pureboot as pb
+
+    os.makedirs(workdir, exist_ok=True)
+    dump = os.path.join(workdir, "dump.bin")
+
+    # Reset boots the application on a BOOTRST-unprogrammed mega; its 'L' is
+    # the loader entry this test needs, reached without a reset.
+    device = pbsim.Device(device_bin, elf, mcu, hz, base_hex, page, baud, dump, reset_hex="0")
+    try:
+        port = pb.Port(device.pty, baud)
+        loader = pb.Loader(port)
+        loader.connect(25)
+
+        # Install the application and hand over to it.
+        pb.op_flash(loader, app_bin, erase=False, verify=True)
+        loader.run_application()
+        if port.read_exact(3, 5.0) != b"APP":
+            fail("the application did not start")
+
+        port.write(b"D")
+        if port.read_exact(1, 5.0) != b"D":
+            fail("the application did not acknowledge dirtying the page buffer")
+        port.write(b"L")
+        loader = pb.Loader(port)
+        loader.connect(25)
+
+        # Program by hand, so the corruption is observable before anything
+        # repairs it.
+        pages = pb.plan_flash(open(app_bin, "rb").read(), loader.info)
+        for address in sorted(pages):
+            loader.write_page(address, pages[address])
+        try:
+            pb.verify_pages(loader, pages)
+        except pb.Error as error:
+            if "verify failed" not in str(error):
+                fail(f"the read-back failed, but not at verify: {error}")
+        else:
+            # Either the fixture no longer dirties the buffer, or the loader
+            # clears it again — in which case this test's premise is gone.
+            fail("programming over a dirty page buffer came back clean")
+
+        # What the programming path uses: one rewrite settles it, and it stays
+        # settled.
+        pb.verify_pages(loader, pages, repair=True)
+        pb.verify_pages(loader, pages)
+
+        # Ground truth beyond the loader's own read-back.
+        loader.run_application()
+        if port.read_exact(3, 5.0) != b"APP":
+            fail("the application did not start after the recovered write")
+        port.close()
+    finally:
+        device.stop()
+    print("pbdirty: a dirty page buffer is caught by verify and cleared by the retry")
+
+
+if __name__ == "__main__":
+    main()

test/pbrehome.py

@@ -1,19 +1,13 @@
 #!/usr/bin/env python3
-"""Re-homing acceptance test: a pureboot image programmed somewhere other
-than its canonical top slot must still be a working loader —
-position-independent, guarding its accidental slot — and the ordinary
+"""Re-homing acceptance test: an image programmed somewhere other than its
+canonical slot must still be a working loader, and the ordinary
 --update-loader flow must put a build into the top slot from there.
 
-Two positions are exercised. Address 0 (a raw .bin handed to a programmer,
-which defaults to offset 0): the staging install and the word-0 redirect
-both run from copies whose slots are not page 0's, so the running-slot
-guard never blocks the flow. The staging slot itself: a loader already
-sitting there IS the installed staging copy — the tool recognizes it by
-its embedded info block and leaves it in place instead of tripping the
-copy's own guard on the composed through-word — and that (older) copy
-streams the new resident like any staged copy. In both cases flashing an
-application through the healed resident overwrites the stale copy, vector
-surgery included, and the banner proves the launch.
+Two positions. Address 0, a raw .bin handed to a programmer: the staging
+install and the word-0 redirect run from copies outside page 0's slot, so the
+running-slot guard never blocks them. And the staging slot itself, where a
+loader already sitting there IS the staging copy — recognized by its embedded
+block and left in place, then streaming the new resident like any staged copy.
 
 Usage: pbrehome.py <device_bin> <pureboot_elf> <update_bin> <mcu> <hz>
                    <base_hex> <page> <baud> <app_bin> <tool_py> <workdir>
@@ -90,7 +84,7 @@ def main():
     # The staging slot: erased flash with the loader sitting exactly where
     # a staging copy would — the tool must leave it in place and let it
     # stream the (different) update build into the resident slot.
-    stage = base - 512
+    stage = base - pb.SLOT
     rehome_from(pbsim, pb, device_bin, elf, hex(stage), hex(stage), update_bin, base, page, baud, app_bin, workdir,
                 mcu, hz)
     print("re-home from the staging slot: converged")

test/pbreloc.py

@@ -1,11 +1,9 @@
 #!/usr/bin/env python3
-"""Position-independence acceptance test: the identical pureboot binary,
-flashed one slot below the resident loader, must serve the complete command
-set from there. The resident installs it (through-word composed by the host
-layer), 'J' transfers control, and every command is exercised against the
-staged copy — the info block must come back byte-identical, the write guard
-must protect the staged copy's own slot and permit the resident's, and the
-staged copy must be able to rewrite the resident slot verbatim.
+"""Position-independence acceptance test: the identical binary, flashed one
+slot below the resident, must serve the complete command set from there. The
+info block must come back byte-identical, the write guard must refuse the
+staged copy's own slot and permit the resident's, and the staged copy must be
+able to rewrite the resident verbatim.
 
 Usage: pbreloc.py <device_bin> <pureboot_elf> <mcu> <hz> <base_hex> <page>
                   <baud> <tool_py> <workdir>
@@ -66,8 +64,10 @@ def main():
         if loader.read_eeprom(0, len(pattern)) != pattern:
             fail("EEPROM round-trip through the staged copy")
 
-        # The guard, both ways: its own slot refused (drained, unchanged),
-        # the resident slot writable.
+        # The guard, both ways: its own slot refused (drained, unchanged), the
+        # resident slot writable. The refusal leaves its drained words in the
+        # SPM buffer, so the write that follows may take them — and clears
+        # them by writing, so the retry must not.
         before = loader.read_flash(stage, page)
         loader.write_page(stage, bytes(page))
         if loader.read_flash(stage, page) != before:
@@ -75,11 +75,13 @@ def main():
         marker = bytes((i * 3) & 0xFF for i in range(page))
         loader.write_page(base, marker)
         if loader.read_flash(base, page) != marker:
-            fail("the staged copy could not write the resident slot")
+            loader.write_page(base, marker)
+            if loader.read_flash(base, page) != marker:
+                fail("the staged copy could not write the resident slot, even on retry")
 
         # Restore the resident image through the staged copy, then 'J' back
         # into it and prove it lives.
-        resident = image + b"\xff" * (info.slot - len(image))
+        resident = image + b"\xff" * (pb.SLOT - len(image))
         pb.write_differing(loader, base, resident)
         back_info = loader.enter_copy(base, 25)
         if back_info.raw != resident_info:

test/pbsim.py

@@ -8,8 +8,11 @@ import subprocess
 
 
 class Device:
-    def __init__(self, binary, elf, mcu, hz, base_hex, page, baud, dump, reset_hex=None, resume=None):
-        cmd = [binary, elf, mcu, hz, base_hex, str(page), str(baud), dump]
+    def __init__(self, binary, elf, mcu, hz, base_hex, page, baud, dump, reset_hex=None, resume=None, link=None):
+        cmd = [binary]
+        if link:
+            cmd += ["-l", link]
+        cmd += [elf, mcu, hz, base_hex, str(page), str(baud), dump]
         if reset_hex is not None or resume is not None:
             # Chips without a hardware boot section — the tinies and the
             # m48s — reset to address 0 like silicon; the boot-sectioned

test/pbtest.py

@@ -1,19 +1,17 @@
 #!/usr/bin/env python3
-"""End-to-end pureboot protocol test: spawn the simavr device, then drive it
-with the real host tool (pureboot.py, as a subprocess over the device's pty)
-through flash + EEPROM + fuse + hand-over scenarios, and cross-check
-the tool's view against the simulator's ground-truth memory dumps.
+"""End-to-end protocol test: drive the simavr device with the real host tool
+over its pty through flash, EEPROM, fuse and hand-over scenarios, and
+cross-check the tool's view against the simulator's ground-truth dumps.
 
 Usage: pbtest.py <device_bin> <pureboot_elf> <mcu> <hz> <base_hex> <page>
-                 <baud> <eeprom_size> <app_bin> <tool_py> <workdir>
-Exits 0 if every scenario passes.
+                 <baud> <eeprom_size> <app_bin> <tool_py> <workdir> [link]
+
+The optional link is the runner's -l spec (usart1, sw:B5,B1, ...), for a
+loader built off the chip's natural serial default.
 """
 
 import os
-import signal
-import subprocess
 import sys
-import time
 
 
 def fail(message):
@@ -33,53 +31,14 @@ def rjmp_decode(word, at, flash_words):
     return (at + 1 + offset) % flash_words
 
 
-class Device:
-    def __init__(self, binary, elf, mcu, hz, base, page, baud, dump):
-        self.proc = subprocess.Popen(
-            [binary, elf, mcu, hz, base, str(page), str(baud), dump],
-            stdout=subprocess.PIPE,
-            stderr=subprocess.STDOUT,
-            text=True,
-        )
-        self.dump = dump
-        self.pty = None
-        deadline = time.time() + 5
-        while time.time() < deadline:
-            line = self.proc.stdout.readline()
-            if not line:
-                break
-            if line.startswith("PB_PTY"):
-                self.pty = line.split()[1]
-                break
-        if not self.pty:
-            self.stop()
-            raise RuntimeError("device did not report a pty")
-
-    def stop(self):
-        self.proc.terminate()
-        try:
-            self.proc.wait(timeout=3)
-        except subprocess.TimeoutExpired:
-            self.proc.kill()
-
-
-def run_tool(tool, pty, baud, *args):
-    result = subprocess.run(
-        [sys.executable, tool, "--port", pty, "--baud", str(baud), "--wait", "20", *args],
-        capture_output=True,
-        text=True,
-        timeout=120,
-    )
-    print(result.stdout, end="")
-    if result.returncode != 0:
-        fail(f"tool exited {result.returncode}: {result.stderr.strip()}")
-    return result.stdout
-
-
 def main():
-    (device_bin, elf, mcu, hz, base_hex, page, baud, eeprom_size, app_bin, tool, workdir) = sys.argv[1:]
+    args = sys.argv[1:]
+    link = args.pop() if len(args) == 12 else None
+    (device_bin, elf, mcu, hz, base_hex, page, baud, eeprom_size, app_bin, tool, workdir) = args
     base, page, baud, eeprom_size = int(base_hex, 0), int(page), int(baud), int(eeprom_size)
     sys.path.insert(0, os.path.dirname(os.path.abspath(tool)))
+    sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
+    import pbsim
     import pureboot as pb
 
     os.makedirs(workdir, exist_ok=True)
@@ -96,27 +55,27 @@ def main():
     # the page byte is the wire's 0-means-256.
     mega = mcu.startswith("atmega")
     patch = not mega or mcu.startswith("atmega48")
-    word_flash = base + 512 > 0x10000
+    word_flash = base + pb.SLOT > 0x10000
     wire_base = base // 2 if word_flash else base
     flags = (1 if patch else 0) | (2 if word_flash else 0)
     info = pb.Info(
-        bytes([ord("P"), ord("B"), 1, 0, 0, 0, page & 0xFF])
+        bytes([ord("P"), ord("B"), pb.NEWEST_LOADER, 0, 0, 0, page & 0xFF])
         + bytes([wire_base & 0xFF, wire_base >> 8, eeprom_size & 0xFF, eeprom_size >> 8])
         + bytes([flags])
     )
 
-    device = Device(device_bin, elf, mcu, hz, base_hex, page, baud, dump)
+    device = pbsim.Device(device_bin, elf, mcu, hz, base_hex, page, baud, dump, link=link)
     try:
         # Session 1: knock from reset, identify, program everything, stay.
-        out = run_tool(tool, device.pty, baud, "--info", "--fuses", "--flash", app_bin,
+        out = pbsim.run_tool(tool, device.pty, baud, "--info", "--fuses", "--flash", app_bin,
                              "--eeprom", ee_path, "--stay")
-        for needed in ("device: signature", "fuses:", "verify:", "stays"):
+        for needed in ("version", "signature", "fuses", "verify:", "stays"):
             if needed not in out:
                 fail(f"session 1 output lacks {needed!r}")
 
         # Session 2: reconnect into the live session, verify, dump, hand over
         # is deferred — the pty must be reopened for the APP banner first.
-        out = run_tool(tool, device.pty, baud, "--verify-flash", app_bin, "--verify-eeprom", ee_path,
+        out = pbsim.run_tool(tool, device.pty, baud, "--verify-flash", app_bin, "--verify-eeprom", ee_path,
                              "--read-flash", read_flash, "--read-eeprom", read_eeprom, "--stay")
         if out.count("verify:") != 2:
             fail("session 2 did not verify both memories")
@@ -136,11 +95,27 @@ def main():
         # runner resets them to address 0 like silicon) or BOOTRST (mega).
         # The loader must answer a fresh knock, and the 'J' hand-over must
         # land in the application, which banners on the same link.
-        device.proc.send_signal(signal.SIGUSR1)
+        device.reset()
         port = pb.Port(device.pty, baud)
         try:
             loader = pb.Loader(port)
-            loader.connect(15)
+            live = loader.connect(15)
+            # The loader built from this tree and the tool beside it must
+            # agree on where the version numbering stands: a bump the tool
+            # was never told about is a loader it would refuse to speak to.
+            if live.version != pb.NEWEST_LOADER:
+                fail(f"loader reports pureboot {live.version}, the tool's newest is {pb.NEWEST_LOADER}")
+
+            # A W addressed inside a page rather than at its base must still
+            # consume exactly one page and prompt. The loader's own slot is
+            # the target — it is drained and never programmed — and the
+            # payload is erased-state bytes, so the probe can disturb neither
+            # the image nor the page buffer it leaves behind.
+            wire = wire_base + 1
+            port.write(bytes((ord("W"), wire & 0xFF, wire >> 8)) + b"\xff" * page)
+            if port.read_exact(1, 5.0) != pb.PROMPT:
+                fail("unaligned W did not return to the prompt")
+
             loader.run_application()
             banner = port.read_exact(3, 5.0)
             if banner != b"APP":
@@ -161,7 +136,7 @@ def main():
     # loader, the trampoline on the application's own entry (patched-vector
     # chips only — a boot-sectioned mega's word 0 stays the application's).
     if patch:
-        flash_words = (base + 512) // 2
+        flash_words = (base + pb.SLOT) // 2
         app = open(app_bin, "rb").read()
         word0 = flash_true[0] | (flash_true[1] << 8)
         if rjmp_decode(word0, 0, flash_words) != base // 2:

test/pbupdate.py

@@ -1,17 +1,12 @@
 #!/usr/bin/env python3
-"""Self-update end-to-end: an application is flashed, then the loader
-replaces itself with a re-timed build through the host tool's
---update-loader — and the power-fail phases of that update are rehearsed by
-killing the simulated device mid-write, restarting it from its flash dump,
-and letting a re-run complete the update.
+"""Self-update end-to-end: an application is flashed, the loader replaces
+itself with a re-timed build, and every power-fail phase is rehearsed by
+killing the device mid-write, restarting it from its flash dump, and letting
+a re-run complete the update.
 
-The boot-sectioned megas run the BOOTRST-unprogrammed profile (reset boots
-the application; the fixture application's 'L' jump is the application-owned
-loader entry), with --assume-fuses standing in for the fuse read simavr
-cannot model. The patched-vector chips — the tinies and the m48s — reset
-into a loader at every phase by construction: the t13a because its staging
-slot carries the reset vector itself, the others through the word-0 redirect
-the tool plants around the resident rewrite.
+The boot-sectioned megas run the BOOTRST-unprogrammed profile — reset boots
+the application, whose 'L' is the application-owned loader entry — with
+--assume-fuses standing in for the fuse read simavr cannot model.
 
 Usage: pbupdate.py <device_bin> <pureboot_elf> <update_elf> <mcu> <hz>
                    <base_hex> <page> <baud> <app_bin> <tool_py> <workdir>
@@ -50,7 +45,7 @@ def assumed_fuses(pb, image):
     image's embedded signature."""
     info = pb.image_info(image)
     which, ladder = pb.BOOT_FUSE[bytes(info.signature[1:3])]
-    bits = min((b for b in ladder if ladder[b] * 2 >= 2 * info.slot), key=lambda b: ladder[b])
+    bits = min((b for b in ladder if ladder[b] * 2 >= 2 * pb.SLOT), key=lambda b: ladder[b])
     fuses = bytearray((0xFF, 0xFF, 0xFF, 0xFF))
     fuses[which] = 0xF8 | (bits << 1) | 1
     return bytes(fuses)
@@ -93,16 +88,13 @@ def main():
     # The m48s are megas without a boot section: patched vector, no fuse
     # preflight, and the same reset-to-0 the tinies get.
     patch = not mega or mcu.startswith("atmega48")
-    # Word-addressed (>64 KiB) chips use the 1 KiB slot; their loader base
-    # itself sits beyond the 16-bit byte space — the 644's base + slot only
-    # touches the 64 KiB boundary and stays byte-addressed.
-    slot = 1024 if base >= 0x10000 and mega else 512
     reset_hex = "0" if mega else None  # the boot-sectioned mega runs BOOTRST-unprogrammed here
     sys.path.insert(0, os.path.dirname(os.path.abspath(tool)))
     sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
     import pbsim
     import pureboot as pb
 
+    slot = pb.SLOT
     os.makedirs(workdir, exist_ok=True)
     objcopy = os.environ.get("PB_OBJCOPY", "avr-objcopy")
     images = {}

test/pureboot_device.c

@@ -1,12 +1,16 @@
-// simavr "device" for the pureboot protocol tests, all three chips. Loads
-// the boot-linked ELF at the loader base, starts execution there (BOOTRST /
-// the patched vector are not what is under test), and exposes the loader's
+// simavr "device" for the pureboot protocol tests, every chip. Loads the
+// boot-linked ELF at the loader base, starts execution there (BOOTRST / the
+// patched vector are not what is under test), and exposes the loader's
 // serial link as a pty for the real host tool:
 //
-//   - Megas: the hardware USART through simavr's uart_pty.
-//   - Tinies: an 8N1 bridge between a pty and the GPIO software UART
-//     (drives PB0, the loader's RX; decodes PB1, its TX), timed against the
-//     simulated cycle counter.
+//   - Hardware USART builds: simavr's uart_pty on the selected instance.
+//   - Software UART builds: an 8N1 bridge between a pty and the GPIO pins,
+//     timed against the simulated cycle counter (drives the loader's RX,
+//     decodes its TX).
+//
+// The link follows the chip's natural default (USART0 on the megas, the
+// software UART on PB0/PB1 elsewhere) unless -l overrides it: `-l usart1`
+// for the second instance, `-l sw:B5,B1` for a software build's RX,TX pins.
 //
 // simavr's tiny cores decode the SPM opcode but attach no NVM module — SPM
 // is a silent no-op (the mega's boot section has one, avr_flash). The
@@ -38,11 +42,31 @@
 
 static avr_t *avr;
 static uart_pty_t uart_pty;
-static int use_uart_pty;
+static int link_software;
+static char uart_digit = '0';
+static char sw_rx_port = 'B', sw_tx_port = 'B';
+static int sw_rx_bit = 0, sw_tx_bit = 1;
 static const char *dump_path;
 static uint32_t reset_pc;
 static volatile sig_atomic_t reset_requested;
 
+static int parse_link(const char *spec)
+{
+	if (strcmp(spec, "usart0") == 0 || strcmp(spec, "usart1") == 0) {
+		link_software = 0;
+		uart_digit = spec[5];
+		return 0;
+	}
+	if (strncmp(spec, "sw", 2) == 0) {
+		link_software = 1;
+		if (spec[2] == '\0')
+			return 0;
+		if (sscanf(spec + 2, ":%c%d,%c%d", &sw_rx_port, &sw_rx_bit, &sw_tx_port, &sw_tx_bit) == 4)
+			return 0;
+	}
+	return -1;
+}
+
 // simavr 1.6's avr_flash PGERS handler erases spm_pagesize bytes starting at
 // Z & ~1 instead of the page containing Z (its PGWRT path masks correctly) —
 // hardware ignores the in-page bits (§26.8.1), so an erase issued with Z
@@ -273,29 +297,42 @@ static void finish(int sig)
 			}
 		}
 	}
-	if (use_uart_pty)
+	if (!link_software)
 		uart_pty_stop(&uart_pty);
 	_exit(0);
 }
 
 int main(int argc, char *argv[])
 {
-	if (argc < 8 || argc > 10) {
+	int link_given = 0;
+	for (int opt; (opt = getopt(argc, argv, "l:")) != -1;) {
+		if (opt != 'l' || parse_link(optarg) != 0) {
+			fprintf(stderr, "device: bad link spec (usart0, usart1, sw, or sw:B0,B1 as RX,TX)\n");
+			return 2;
+		}
+		link_given = 1;
+	}
+	int args = argc - optind;
+	if (args < 7 || args > 9) {
 		fprintf(stderr,
-		        "usage: %s <pureboot.elf> <mcu> <hz> <base_hex> <page> <baud> <flash_dump>"
+		        "usage: %s [-l link] <pureboot.elf> <mcu> <hz> <base_hex> <page> <baud> <flash_dump>"
 		        " [reset_hex] [resume_flash]\n"
-		        "  reset_hex:    reset vector (default: base on the mega, 0 on the tinies)\n"
+		        "  -l link:      usart0 | usart1 | sw[:B0,B1] (RX,TX); default: the chip's own\n"
+		        "  reset_hex:    reset vector (default: base with a boot section, else 0)\n"
 		        "  resume_flash: raw full-flash image loaded instead of the ELF — a prior\n"
 		        "                run's dump, for power-fail resume tests\n",
 		        argv[0]);
 		return 2;
 	}
+	argv += optind - 1; // argv[1] is the ELF again, whatever was parsed
 	const char *mcu_name = argv[2];
 	uint32_t base = (uint32_t)strtoul(argv[4], NULL, 0);
 	unsigned page = (unsigned)atoi(argv[5]);
 	unsigned baud = (unsigned)atoi(argv[6]);
 	dump_path = argv[7];
-	use_uart_pty = strncmp(mcu_name, "atmega", 6) == 0; // every mega links over its hardware USART
+	int is_mega = strncmp(mcu_name, "atmega", 6) == 0;
+	if (!link_given)
+		link_software = !is_mega; // the chips' natural links: USART0, or PB0/PB1
 
 	avr = avr_make_mcu_by_name(mcu_name);
 	if (!avr) {
@@ -306,7 +343,7 @@ int main(int argc, char *argv[])
 	avr->frequency = (uint32_t)strtoul(argv[3], NULL, 0);
 	memset(avr->flash, 0xff, avr->flashend + 1); // real flash powers up erased
 
-	if (argc > 9) {
+	if (args > 8) {
 		// Resume: the full flash image of an interrupted prior run.
 		FILE *f = fopen(argv[9], "rb");
 		if (!f || fread(avr->flash, 1, avr->flashend + 1, f) == 0) {
@@ -327,8 +364,8 @@ int main(int argc, char *argv[])
 	// and the boot-section-less m48s reset to word 0 like silicon — erased
 	// flash walks up into the loader, and after the host's surgery the
 	// patched vector routes there.
-	int boot_section = use_uart_pty && strncmp(mcu_name, "atmega48", 8) != 0;
-	reset_pc = argc > 8 ? (uint32_t)strtoul(argv[8], NULL, 0) : (boot_section ? base : 0);
+	int boot_section = is_mega && strncmp(mcu_name, "atmega48", 8) != 0;
+	reset_pc = args > 7 ? (uint32_t)strtoul(argv[8], NULL, 0) : (boot_section ? base : 0);
 	avr->pc = reset_pc;
 	avr->codeend = avr->flashend;
 
@@ -341,27 +378,34 @@ int main(int argc, char *argv[])
 		avr_ioctl(avr, AVR_IOCTL_EEPROM_SET, &seed);
 	}
 
-	if (use_uart_pty) {
+	// The megas carry simavr's avr_flash module (and its two gaps the wrap
+	// above fixes); the tinies get the NVM module simavr lacks. Which serial
+	// bridge runs is the link's business, not the chip class's.
+	if (is_mega) {
 		fix_mega_flash_erase();
-		// POLL_SLEEP paces an idle-polling loader in host real time (a
-		// no-hardware CPU-saving hack); clear it so cycles run free.
-		uint32_t flags = 0;
-		avr_ioctl(avr, AVR_IOCTL_UART_GET_FLAGS('0'), &flags);
-		flags &= ~AVR_UART_FLAG_POLL_SLEEP;
-		avr_ioctl(avr, AVR_IOCTL_UART_SET_FLAGS('0'), &flags);
-		uart_pty_init(avr, &uart_pty);
-		uart_pty_connect(&uart_pty, '0');
-		printf("PB_PTY %s\n", uart_pty.pty.slavename);
 	} else {
 		nvm.page = page;
 		memset(nvm.buffer, 0xff, sizeof(nvm.buffer));
 		nvm.io.kind = "tiny_nvm";
 		nvm.io.ioctl = nvm_ioctl;
 		avr_register_io(avr, &nvm.io);
+	}
 
+	if (!link_software) {
+		// POLL_SLEEP paces an idle-polling loader in host real time (a
+		// no-hardware CPU-saving hack); clear it so cycles run free.
+		uint32_t flags = 0;
+		avr_ioctl(avr, AVR_IOCTL_UART_GET_FLAGS(uart_digit), &flags);
+		flags &= ~AVR_UART_FLAG_POLL_SLEEP;
+		avr_ioctl(avr, AVR_IOCTL_UART_SET_FLAGS(uart_digit), &flags);
+		uart_pty_init(avr, &uart_pty);
+		uart_pty_connect(&uart_pty, uart_digit);
+		printf("PB_PTY %s\n", uart_pty.pty.slavename);
+	} else {
 		bit_cycles = (avr->frequency + baud / 2) / baud; // matches uart.hpp's own rounding exactly
-		rx_pin = avr_io_getirq(avr, AVR_IOCTL_IOPORT_GETIRQ('B'), 0);
-		avr_irq_register_notify(avr_io_getirq(avr, AVR_IOCTL_IOPORT_GETIRQ('B'), 1), tx_hook, NULL);
+		rx_pin = avr_io_getirq(avr, AVR_IOCTL_IOPORT_GETIRQ(sw_rx_port), (unsigned)sw_rx_bit);
+		avr_irq_register_notify(avr_io_getirq(avr, AVR_IOCTL_IOPORT_GETIRQ(sw_tx_port), (unsigned)sw_tx_bit), tx_hook,
+		                        NULL);
 		avr_raise_irq(rx_pin, 1); // idle line
 
 		int slave;
@@ -389,18 +433,27 @@ int main(int argc, char *argv[])
 			reset_requested = 0;
 			avr_reset(avr);
 			avr->pc = reset_pc;
-			if (use_uart_pty) { // reset restores the pacing hack; re-clear it
+			if (!link_software) { // reset restores the pacing hack; re-clear it
 				uint32_t flags = 0;
-				avr_ioctl(avr, AVR_IOCTL_UART_GET_FLAGS('0'), &flags);
+				avr_ioctl(avr, AVR_IOCTL_UART_GET_FLAGS(uart_digit), &flags);
 				flags &= ~AVR_UART_FLAG_POLL_SLEEP;
-				avr_ioctl(avr, AVR_IOCTL_UART_SET_FLAGS('0'), &flags);
+				avr_ioctl(avr, AVR_IOCTL_UART_SET_FLAGS(uart_digit), &flags);
 			} else {
 				bridge_reset();
 			}
 		}
-		if (!use_uart_pty && ++since_poll >= 2000) {
+		if (link_software && ++since_poll >= 2000) {
 			since_poll = 0;
 			poll_pty();
+			// An unthrottled idle simulation runs the activation window out
+			// from under the host's real-time knock cadence: a 1 MHz build's
+			// 8 s window is 8 M cycles — tens of wall milliseconds — so a
+			// first knock lost to an in-flight reset misses the window
+			// entirely. Pace the simulation only while the bridge is fully
+			// quiet (nothing decoding, nothing queued); transfers keep full
+			// speed, and a quiet window stretches toward real time.
+			if (!rx_active && !tx_active && rx_head == rx_tail)
+				usleep(200);
 		}
 	}
 	finish(0);

test/test_planner.py

@@ -1,9 +1,8 @@
 #!/usr/bin/env python3
-"""Host-tool unit tests — the pure planning and policy logic, no simulator:
-the flash-programming orders and their recovery properties, the reset-vector
-surgery, the staging-slot composition, the mega boot-fuse decode, and the
-update preflight's error/warning matrix (fuse combinations simavr cannot
-model reach it here as synthetic bytes).
+"""Host-tool unit tests — the planning and policy logic, no simulator:
+programming orders and their recovery properties, the reset-vector surgery,
+the staging composition, the boot-fuse decode, and the update preflight over
+fuse combinations simavr cannot model.
 
 Usage: test_planner.py <tool_py>
 """
@@ -27,14 +26,15 @@ def expect_error(what, fn, *needles):
     fail(f"{what}: no error raised")
 
 
-def info_of(pb, base, page, patch, flash, signature=(0x1E, 0x93, 0x0B), word_flash=False):
+def info_of(pb, base, page, patch, flash, signature=(0x1E, 0x93, 0x0B), word_flash=False, version=None):
     scale = 2 if word_flash else 1
     wire_base = base // scale
     flags = (1 if patch else 0) | (2 if word_flash else 0)
-    raw = bytes((0x50, 0x42, 1, *signature, page & 0xFF, wire_base & 0xFF, wire_base >> 8,
-                 0, 2, flags))
+    raw = bytes((0x50, 0x42, pb.NEWEST_LOADER if version is None else version,
+                 *signature, page & 0xFF, wire_base & 0xFF, wire_base >> 8, 0, 2, flags))
     info = pb.Info(raw)
-    assert info.flash_size == flash
+    if info.flash_size != flash:
+        fail(f"info_of({base:#x}) decodes to {info.flash_size:#x} of flash, not {flash:#x}")
     return info
 
 
@@ -55,6 +55,21 @@ def main():
     tiny = info_of(pb, 0x1E00, 64, True, 0x2000)
     mega = info_of(pb, 0x7E00, 128, False, 0x8000, signature=(0x1E, 0x95, 0x0F))
 
+    # Versioning: the block's third byte is the loader's version, and the tool
+    # speaks a window of them. Every version in the window decodes, so an older
+    # deployed loader stays usable; one above the window is refused by name,
+    # since which version changed the protocol is knowledge only the tool
+    # holds, and it holds none about a version it has never heard of.
+    for version in range(pb.OLDEST_LOADER, pb.NEWEST_LOADER + 1):
+        if info_of(pb, 0x1E00, 64, True, 0x2000, version=version).version != version:
+            fail(f"pureboot {version} does not decode")
+    expect_error(
+        "unknown loader version",
+        lambda: info_of(pb, 0x1E00, 64, True, 0x2000, version=pb.NEWEST_LOADER + 1),
+        f"pureboot {pb.NEWEST_LOADER + 1}",
+        "newer tool",
+    )
+
     # mega_boot: BOOTSZ words and the BOOTRST sense per chip — the fuse byte
     # index (EXTENDED on the x8 line except the m328s' HIGH, HIGH elsewhere)
     # and the per-family ladders (Atmel-2486/2466/2503/2545/8271/DS40002065/
@@ -79,9 +94,7 @@ def main():
         ((0x1E, 0x97, 0x05), 0x20000, 3, {0b11: 0x1FC00, 0b10: 0x1F800, 0b01: 0x1F000, 0b00: 0x1E000}),  # 1284P
     )
     for signature, flash, which, ladder in cases:
-        # Word-addressed chips carry the 1 KiB slot (their smallest boot sector).
-        slot = 1024 if flash > 0x10000 else 512
-        chip = info_of(pb, flash - slot, 128 if flash < 0x20000 else 0, False, flash,
+        chip = info_of(pb, flash - pb.SLOT, 128 if flash < 0x20000 else 0, False, flash,
                        signature=signature, word_flash=flash > 0x10000)
         for bits, start in ladder.items():
             fuses = bytearray((0xFF, 0xFF, 0xFF, 0xFF))
@@ -94,10 +107,12 @@ def main():
             if prog or at != start:
                 fail(f"mega_boot {signature[1]:02x}{signature[2]:02b} unprogrammed: {prog} {at:#07x}")
 
-    # Word-addressed info decode: the 1284P's base/page ride the wire scaled,
-    # and its slot is 1 KiB.
-    big = info_of(pb, 0x1FC00, 0, False, 0x20000, signature=(0x1E, 0x97, 0x05), word_flash=True)
-    if big.page != 256 or big.base != 0x1FC00 or big.stage != 0x1F800 or big.slot != 1024:
+    # Word-addressed info decode: the 1284P's base and page ride the wire
+    # scaled — a 17-bit base halved into the block's two bytes, a 256-byte page
+    # spelled 0 — and its slot is the same 512 bytes as everywhere else, so its
+    # staging slot lands inside the 1 KiB minimum boot section.
+    big = info_of(pb, 0x1FE00, 0, False, 0x20000, signature=(0x1E, 0x97, 0x05), word_flash=True)
+    if big.page != 256 or big.base != 0x1FE00 or big.stage != 0x1FC00:
         fail(f"word-addressed info decode: page {big.page}, base {big.base:#x}, stage {big.stage:#x}")
 
     # Surgery: word 0 lands on the loader, the trampoline on the original
@@ -154,6 +169,12 @@ def main():
         fail("image_info misses the embedded block")
     if pb.image_info(bytes((0xAA,)) * 40) is not None:
         fail("image_info invents a block")
+    # An older loader's image stays readable, so a deployed build can be
+    # identified and installed like any other.
+    old = info_of(pb, 0x1E00, 64, True, 0x2000, version=pb.OLDEST_LOADER)
+    found_old = pb.image_info(bytes((0xAA,)) * 10 + old.raw)
+    if found_old is None or found_old.version != pb.OLDEST_LOADER:
+        fail("image_info misses an older loader's block")
 
     # loader_image must peel a padded image down to the slot content: a raw
     # .bin padded from address 0 (or a whole-flash read-back with the loader
@@ -194,6 +215,15 @@ def main():
     if pb.update_preflight(bytes((0xAA,)) * 8 + tiny.raw, tiny, None) != []:
         fail("tiny preflight should pass without fuses")
 
+    # The 1284s' smallest boot section (512 words) is exactly the resident
+    # slot plus its staging slot, so self-update is possible at the minimum
+    # BOOTSZ — no fuse step up, the 644's geometry. That holds only while a
+    # slot is 512 B: at 1 KiB the staging slot would fall outside the section
+    # and the preflight would refuse.
+    notes = pb.update_preflight(bytes((0xAA,)) * 8 + big.raw, big, fuses(0xFE))
+    if not any("staging slot" in n for n in notes):
+        fail(f"1284 minimum-BOOTSZ notes: {notes}")
+
     # The walk-region refusal: BOOTRST aimed below the loader plus app data
     # in the walk span errors without --force; erased spans and unprogrammed
     # BOOTRST pass.
@@ -204,6 +234,114 @@ def main():
     pb.check_walk_region({0x7800: bytes((0xFF,)) * 128}, mega, fuses(0xFA), False)
     pb.check_walk_region(deep, mega, None, False)  # fuses unknown: no check
 
+    # The repairing verify: a mismatched page is rewritten rather than raised,
+    # bounded so a fault that is not self-clearing cannot spin.
+    class FakeLoader:
+        """A device whose first `bad` writes of any page land wrong."""
+
+        def __init__(self, info, bad):
+            self.info = info
+            self.bad = bad
+            self.flash = {}
+            self.writes = 0
+
+        def write_page(self, address, data):
+            self.writes += 1
+            self.flash[address] = bytes(len(data)) if self.bad > 0 else bytes(data)
+            self.bad -= 1
+
+        def read_flash(self, address, count):
+            return self.flash.get(address, bytes(count))
+
+    want = {0: bytes((i * 5) & 0xFF for i in range(128))}
+
+    # One bad write, then good: repaired in place, and the caller never sees
+    # an error. The rewrite is counted, so a silent no-op cannot pass.
+    device = FakeLoader(info_of(pb, 0x7E00, 128, False, 0x8000), bad=1)
+    device.write_page(0, want[0])
+    pb.verify_pages(device, want, repair=True)
+    if device.writes != 2:
+        fail(f"repairing verify made {device.writes} writes, expected 2")
+
+    # Without repair the same state raises, so the repair is what fixed it.
+    device = FakeLoader(info_of(pb, 0x7E00, 128, False, 0x8000), bad=1)
+    device.write_page(0, want[0])
+    expect_error("verify without repair", lambda: pb.verify_pages(device, want), "verify failed")
+
+    # A page that never comes good stops after RETRIES rewrites, and says so.
+    device = FakeLoader(info_of(pb, 0x7E00, 128, False, 0x8000), bad=99)
+    device.write_page(0, want[0])
+    expect_error(
+        "unrepairable page",
+        lambda: pb.verify_pages(device, want, repair=True),
+        "verify failed",
+        f"after {pb.RETRIES} retries",
+    )
+    if device.writes != pb.RETRIES + 1:
+        fail(f"unrepairable page took {device.writes} writes, expected {pb.RETRIES + 1}")
+
+    # The knock handshake against a device that is not listening yet — the
+    # state a port open leaves behind: it resets the chip into a fresh
+    # activation window while the previous session's prompt is still in
+    # flight, so the first knock is lost and a prompt arrives anyway.
+    class FakePort:
+        """A loader in its activation window, plus `lost` leading writes the
+        reset swallows and one stale prompt still on the wire."""
+
+        def __init__(self, info_raw, lost=0, stale=b"", active=False):
+            self.info_raw = info_raw
+            self.lost = lost
+            self.inflight = bytearray(stale)
+            self.rx = bytearray()
+            self.active = active
+            self.last = None
+
+        def flush_input(self):
+            self.rx.clear()
+
+        def write(self, data):
+            if self.lost:
+                self.lost -= 1
+                return
+            for byte in bytes(data):
+                if not self.active:
+                    self.active = self.last == ord("p") and byte == ord("b")
+                    self.last = byte
+                    if self.active:
+                        self.rx += pb.PROMPT
+                elif byte == ord("b"):
+                    self.rx += self.info_raw + pb.PROMPT
+                else:
+                    self.rx += pb.PROMPT
+
+        def read_available(self, wait):
+            self.rx = self.inflight + self.rx  # the stale prompt lands late
+            self.inflight.clear()
+            out, self.rx = bytes(self.rx), bytearray()
+            return out
+
+        def read_exact(self, count, timeout):
+            if len(self.rx) < count:
+                raise pb.Error(f"timeout: got {len(self.rx)} of {count} bytes")
+            out, self.rx = bytes(self.rx[:count]), self.rx[count:]
+            return out
+
+    raw = info_of(pb, 0x7E00, 128, False, 0x8000).raw
+    for what, port in (
+        ("clean window", FakePort(raw)),
+        ("stale prompt over a lost knock", FakePort(raw, lost=1, stale=pb.PROMPT)),
+        ("live session", FakePort(raw, active=True)),
+    ):
+        info = pb.Loader(port).connect(5)
+        if info.raw != raw:
+            fail(f"connect ({what}) returned {info.raw.hex()}")
+
+    # A device that never answers still says so, and a version the tool cannot
+    # speak is reported as such rather than retried into a timeout.
+    expect_error("dead device", lambda: pb.Loader(FakePort(raw, lost=99)).connect(0), "no answer")
+    old = bytes(raw[:2]) + bytes((pb.NEWEST_LOADER + 1,)) + bytes(raw[3:])
+    expect_error("unspeakable version", lambda: pb.Loader(FakePort(old)).connect(5), "needs a newer tool")
+
     print("test_planner: all planner and policy checks pass")
 
 

tools/check.sh

@@ -0,0 +1,39 @@
+#!/bin/bash
+# The port's gate: every chip's generated workflow — build, size matrix, and
+# the simulator-driven protocol suites. --full adds the reflect-spot builds
+# (libavr's rule: reflect compiles are bounded to its spot set, never the
+# full matrix) and swaps the compact size matrix for the exhaustive
+# clock × baud × backend cross product. LIBAVR_ROOT must point at the libavr
+# checkout.
+set -e
+cd "$(dirname "$0")/.."
+
+full=0
+[[ "$1" == "--full" ]] && { full=1; shift; export PUREBOOT_FULL_MATRIX=1; }
+
+CHIPS=(attiny13 attiny13a attiny25 attiny45 attiny85
+       atmega8 atmega8a atmega16 atmega16a atmega32 atmega32a
+       atmega48 atmega48a atmega48p atmega48pa
+       atmega88 atmega88a atmega88p atmega88pa
+       atmega168 atmega168a atmega168p atmega168pa
+       atmega328 atmega328p
+       atmega164a atmega164p atmega164pa
+       atmega324a atmega324p atmega324pa
+       atmega644 atmega644a atmega644p atmega644pa
+       atmega1284 atmega1284p)
+REFLECT_SPOT=(attiny13a attiny85 atmega8 atmega16a atmega32a atmega48pa
+              atmega88 atmega168pa atmega328p atmega164a atmega644p atmega1284)
+
+for chip in "${CHIPS[@]}"; do
+	echo "==== $chip ===="
+	cmake --workflow --preset "$chip-generated" "$@"
+done
+
+if ((full)); then
+	for chip in "${REFLECT_SPOT[@]}"; do
+		echo "==== $chip reflect ===="
+		cmake --workflow --preset "$chip-reflect" "$@"
+	done
+fi
+
+echo "check: every chip green"

tools/make_presets.py

@@ -0,0 +1,90 @@
+#!/usr/bin/env python3
+"""Regenerate CMakePresets.json — one uniform pipeline per chip.
+
+Every chip gets generated-mode configure/build/test presets and a workflow
+running all three. Reflect-mode presets (configure + build, no tests — the
+port's TUs compile identically; the sims prove nothing new there) exist for
+libavr's reflect spot set only, mirroring its rule: the full reflect matrix
+is never built, one chip per hardware class and pack vintage is.
+
+Run from the repo root: tools/make_presets.py
+"""
+
+import json
+import os
+
+CHIPS = [
+    "attiny13", "attiny13a", "attiny25", "attiny45", "attiny85",
+    "atmega8", "atmega8a", "atmega16", "atmega16a", "atmega32", "atmega32a",
+    "atmega48", "atmega48a", "atmega48p", "atmega48pa",
+    "atmega88", "atmega88a", "atmega88p", "atmega88pa",
+    "atmega168", "atmega168a", "atmega168p", "atmega168pa",
+    "atmega328", "atmega328p",
+    "atmega164a", "atmega164p", "atmega164pa",
+    "atmega324a", "atmega324p", "atmega324pa",
+    "atmega644", "atmega644a", "atmega644p", "atmega644pa",
+    "atmega1284", "atmega1284p",
+]
+
+# libavr's REFLECT_SPOT (tools/check.sh): one chip per hardware class and
+# pack vintage.
+REFLECT_SPOT = [
+    "attiny13a", "attiny85", "atmega8", "atmega16a", "atmega32a",
+    "atmega48pa", "atmega88", "atmega168pa", "atmega328p", "atmega164a",
+    "atmega644p", "atmega1284",
+]
+
+
+def main():
+    configure = [{
+        "name": "base",
+        "hidden": True,
+        "generator": "Ninja",
+        "binaryDir": "${sourceDir}/build/${presetName}",
+        "toolchainFile": "$env{LIBAVR_ROOT}/cmake/avr-toolchain.cmake",
+        "cacheVariables": {
+            "CMAKE_BUILD_TYPE": "Release",
+            "CMAKE_EXPORT_COMPILE_COMMANDS": "ON",
+            "CMAKE_COLOR_DIAGNOSTICS": "ON",
+        },
+    }]
+    build, test, workflows = [], [], []
+
+    def add(chip, mode):
+        name = f"{chip}-{mode}"
+        configure.append({
+            "name": name,
+            "inherits": "base",
+            "cacheVariables": {
+                "LIBAVR_MCU": chip,
+                "LIBAVR_REFLECT": "ON" if mode == "reflect" else "OFF",
+            },
+        })
+        build.append({"name": name, "configurePreset": name})
+        steps = [{"type": "configure", "name": name}, {"type": "build", "name": name}]
+        if mode == "generated":
+            test.append({"name": name, "configurePreset": name, "output": {"outputOnFailure": True}})
+            steps.append({"type": "test", "name": name})
+        workflows.append({"name": name, "steps": steps})
+
+    for chip in CHIPS:
+        add(chip, "generated")
+    for chip in REFLECT_SPOT:
+        add(chip, "reflect")
+
+    presets = {
+        "version": 8,
+        "configurePresets": configure,
+        "buildPresets": build,
+        "testPresets": test,
+        "workflowPresets": workflows,
+    }
+    path = os.path.join(os.path.dirname(os.path.abspath(__file__)), "..", "CMakePresets.json")
+    with open(path, "w") as f:
+        json.dump(presets, f, indent=1)
+        f.write("\n")
+    print(f"{len(CHIPS)} chips, {len(REFLECT_SPOT)} reflect: {os.path.normpath(path)}")
+
+
+if __name__ == "__main__":
+    main()