pureboot v8: one-wire on every backend

HALF_DUPLEX deploys a shared line per backend. The hardware USART takes
the library's .half_duplex turn-around — RXD and TXD tied off-chip, each
reply byte held to transmit-complete before the line can be released
(m8 404 B, m328P 440, 1284P 460; the window poll runs through the
outlined release-line call at 18 or 22 cycles a poll, measured off the
built loops and held per chip by pureboot.window.halfduplex). The
software and autobaud links fold onto the RX pin — RX == TX spells the
same — and cost nothing: the frame's direction wrap is what the dropped
second-pin init paid, and the worst image in the space is unchanged at
the 1284s' 502 of 512, now with its one-wire twin proven equal across
the exhaustive matrix. The host gains --one-wire, the echo discard a
shared line requires: the adapter's echo is matched byte for byte and a
reply interleaving a blind write — a loader already in session
re-prompts inside the knock — is held for the reader. The device runner
models the shared line by direction (drives only while the firmware's
DDR reads input, decodes only while the firmware owns it, supplies the
host-side echo), extends the USART pin-ownership model to RXEN's hold
on RXD, and starts the pty USART from the datasheet's zeroed UCSR#B:
simavr's TXEN-set reset plus its clear-UDRE-on-TXEN-drop otherwise
wedges the first transmitter after a receiver-only program, which the
half-duplex window gate caught as a banner that never came. v7 is
tagged at its era's last commit; v8 changes nothing on the wire.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

test/pbtest.py

@@ -11,6 +11,7 @@ loader built off the chip's natural serial default.
 """
 
 import os
+import re
 import sys
 
 
@@ -70,10 +71,15 @@ def main():
         + bytes([flags])
     )
 
+    # A shared-line link (RX == TX in the -l spec) makes the host read every
+    # byte it sends back off the line; all sessions then discard the echo.
+    one_wire = bool(link) and re.fullmatch(r"sw:([A-H][0-7]),\1(@[01])?", link) is not None
+    extra = ("--one-wire",) if one_wire else ()
+
     device = pbsim.Device(device_bin, elf, mcu, hz, base_hex, page, baud, dump, link=link)
     try:
         # Session 1: knock from reset, identify, program everything, stay.
-        out = pbsim.run_tool(tool, device.pty, baud, "--info", "--fuses", "--flash", app_bin,
+        out = pbsim.run_tool(tool, device.pty, baud, *extra, "--info", "--fuses", "--flash", app_bin,
                              "--eeprom", ee_path, "--stay")
         for needed in ("version", "signature", "fuses", "verify:", "stays"):
             if needed not in out:
@@ -83,7 +89,7 @@ def main():
         # the data space; hand over is deferred — the pty must be reopened for
         # the APP banner first.
         probe = "c0ffee"
-        out = pbsim.run_tool(tool, device.pty, baud, "--verify-flash", app_bin, "--verify-eeprom", ee_path,
+        out = pbsim.run_tool(tool, device.pty, baud, *extra, "--verify-flash", app_bin, "--verify-eeprom", ee_path,
                              "--read-flash", read_flash, "--read-eeprom", read_eeprom,
                              "--poke", f"{ram_base:#x}:{probe}", "--peek", f"{ram_base:#x}:3", "--stay")
         if out.count("verify:") != 2:
@@ -111,6 +117,8 @@ def main():
         # land in the application, which banners on the same link.
         device.reset()
         port = pb.Port(device.pty, baud)
+        if one_wire:
+            port = pb.OneWirePort(port)
         try:
             loader = pb.Loader(port)
             live = loader.connect(15)