pureboot: the pin axis, and the mute it was hiding
Pins move the image for exactly one reason — a bit-banged link on a USART's own
pins has to release that USART — and the matrix said outright that they were no
axis, so the tightest configuration in the space was one nothing built. Not
subtly, either: the 1284's slot ends at flash end, so that build does not merely
exceed the size test's limit, it fails to link. pureboot_{sw,autobaud}_on_usart
{0,1} are gate points in both matrix modes now, and the exhaustive sweep carries
the pins across its whole cross product. The hand-measured table is the gate's
output: 506 B of 512 for the 1284 autobaud on USART0's pins, 504 on USART1's.
pureboot.mute drives the defect itself — an application hands over with USART0
still enabled and the loader on those pins must still answer. Reaching that
needed the runner to know an enabled USART owns its TxD, which simavr does not
model at all: it wires a USART through IRQs and never takes the pin from the
port. It also brings UCSRnB up with TXEN already set where silicon clears the
register, so the runner restores the reset value for the USART it models — the
mute must come from the application, not from power-on. The fixture stays
silent, since nothing is listening on the USART it brings up.
test_handshake.py, written where no gate could run it, is pureboot.handshake.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
This commit is contained in:
@@ -157,6 +157,8 @@ if(PROJECT_IS_TOP_LEVEL)
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add_test(NAME pureboot.planner
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/test_planner.py
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${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py)
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add_test(NAME pureboot.handshake
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/test_handshake.py)
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endif()
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# The protocol test flashes this fixture through the loader with the real
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@@ -235,12 +237,12 @@ if(PROJECT_IS_TOP_LEVEL)
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# The size matrix: every configuration axis that could move the image
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# size — the serial backend (different code), the USART instance
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# (different registers), the clock (different constants), and the baud
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# through the shapes its bit timing takes — each combination must still
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# fit the chip's slot budget. Pins are size-neutral (port and bit are
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# immediate operands) and the timeout is a constant, so neither adds an
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# axis. The stock build is one point of this matrix and already has its
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# test.
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# (different registers), the clock (different constants), the baud
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# through the shapes its bit timing takes, and the pins through the one
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# thing they decide (whether a bit-banged link has to release the USART
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# that owns them) — each combination must still fit the chip's slot
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# budget. The timeout is a constant and adds no axis. The stock build is
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# one point of this matrix and already has its test.
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function(pureboot_size_variant name)
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pureboot_add_loader(${name} ${ARGN})
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add_test(NAME ${name}.size
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@@ -258,18 +260,25 @@ if(PROJECT_IS_TOP_LEVEL)
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-DLIMIT=${PUREBOOT_LIMIT} -P ${CMAKE_CURRENT_SOURCE_DIR}/test/check_size.cmake)
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# One point of the exhaustive matrix, named from its resolved parameters
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# so the enumeration cannot collide with itself. Unreachable rates drop
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# out here rather than aborting the configure.
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function(pureboot_matrix_point hz baud link)
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# so the enumeration cannot collide with itself. `pins` is empty for the
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# default pair, or the index of the USART whose own pins a bit-banged
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# link sits on. Unreachable rates drop out here rather than aborting the
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# configure.
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function(pureboot_matrix_point hz baud link pins)
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set(_name pbm_${hz}_${baud}_${link})
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if(link STREQUAL "software")
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pureboot_baud_feasible(${hz} ${baud} 1 _ok)
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set(_args SERIAL software)
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if(NOT pins STREQUAL "")
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list(APPEND _args RX ${PUREBOOT_USART${pins}_RX} TX ${PUREBOOT_USART${pins}_TX})
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set(_name ${_name}_on${pins})
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endif()
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else()
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pureboot_baud_feasible(${hz} ${baud} 0 _ok)
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set(_args USART ${link})
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endif()
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if(_ok)
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pureboot_size_variant(pbm_${hz}_${baud}_${link} CLOCK ${hz} BAUD ${baud} ${_args})
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pureboot_size_variant(${_name} CLOCK ${hz} BAUD ${baud} ${_args})
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endif()
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endfunction()
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@@ -307,12 +316,14 @@ if(PROJECT_IS_TOP_LEVEL)
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if(DEFINED ENV{PUREBOOT_FULL_MATRIX})
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foreach(_matrix_hz IN LISTS _full_clocks)
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foreach(_matrix_baud IN LISTS _full_bauds)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} software)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} software "")
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if(PUREBOOT_HAS_USART)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 0)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} software 0)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 0 "")
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endif()
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if(PUREBOOT_HAS_USART1)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 1)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} software 1)
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pureboot_matrix_point(${_matrix_hz} ${_matrix_baud} 1 "")
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endif()
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endforeach()
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endforeach()
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@@ -331,11 +342,42 @@ if(PROJECT_IS_TOP_LEVEL)
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endforeach()
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list(GET _matrix_clocks -1 _matrix_top_hz)
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pureboot_size_variant(pureboot_sw_wide CLOCK ${_matrix_top_hz} BAUD 9600 SERIAL software)
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# The pin axis at the widest software image — the slowest ladder rate
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# against the fastest clock, whose bit spin needs the 16-bit delay
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# loop — with the USART release on top of it. The exhaustive sweep
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# above carries the same axis across its whole cross product.
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if(PUREBOOT_HAS_USART)
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pureboot_size_variant(pureboot_sw_wide_on_usart0 CLOCK ${_matrix_top_hz} BAUD 9600
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SERIAL software RX ${PUREBOOT_USART0_RX} TX ${PUREBOOT_USART0_TX})
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endif()
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if(PUREBOOT_HAS_USART1)
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pureboot_size_variant(pureboot_sw_wide_on_usart1 CLOCK ${_matrix_top_hz} BAUD 9600
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SERIAL software RX ${PUREBOOT_USART1_RX} TX ${PUREBOOT_USART1_TX})
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endif()
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endif()
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if(PUREBOOT_HAS_USART1)
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pureboot_size_variant(pureboot_usart1 USART 1)
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endif()
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# The pin axis at its fixed points, in both matrix modes. The autobaud
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# loader carries no clock and no baud, so the sweep has nothing to vary
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# for it — yet it is the tightest image in the space, and on a USART's
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# own pins it pays the release too: that combination is the one that
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# overflowed the 1284's slot. The software build on those pins is the
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# same deployment the mute test drives.
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if(PUREBOOT_HAS_USART)
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pureboot_size_variant(pureboot_sw_on_usart0 SERIAL software
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RX ${PUREBOOT_USART0_RX} TX ${PUREBOOT_USART0_TX})
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pureboot_size_variant(pureboot_autobaud_on_usart0 SERIAL autobaud
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RX ${PUREBOOT_USART0_RX} TX ${PUREBOOT_USART0_TX})
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endif()
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if(PUREBOOT_HAS_USART1)
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pureboot_size_variant(pureboot_sw_on_usart1 SERIAL software
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RX ${PUREBOOT_USART1_RX} TX ${PUREBOOT_USART1_TX})
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pureboot_size_variant(pureboot_autobaud_on_usart1 SERIAL autobaud
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RX ${PUREBOOT_USART1_RX} TX ${PUREBOOT_USART1_TX})
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endif()
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# One configured deployment end to end — a real board's shape rather
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# than the stock assumption: the ATmega328P on its shipped 1 MHz fuses,
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# the software UART on hand-picked pins (TX = PB1, RX = PB5), the ladder
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@@ -364,6 +406,33 @@ if(PROJECT_IS_TOP_LEVEL)
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set_tests_properties(pureboot.custom PROPERTIES TIMEOUT 180)
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endif()
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# Hand-over with the USART that owns the loader's pins left enabled — the
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# state an application reaches by jumping in without a reset, and the one
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# that made a bit-banged loader on PD0/PD1 (where the Uno's USB bridge
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# lands) receive and obey while answering nothing. Run where it was found
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# on silicon; the runner supplies the pin ownership simavr has no model
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# for, which is what lets this fail when the release is gone.
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if(LIBAVR_MCU STREQUAL "atmega328p" AND DEFINED PB_DEVICE)
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get_target_property(_mute_hz pureboot_sw_on_usart0 PUREBOOT_HZ)
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get_target_property(_mute_baud pureboot_sw_on_usart0 PUREBOOT_BAUD)
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get_target_property(_mute_link pureboot_sw_on_usart0 PUREBOOT_LINK)
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add_executable(pbapp_handover test/pbapp.cpp)
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target_link_libraries(pbapp_handover PRIVATE libavr)
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target_compile_definitions(pbapp_handover PRIVATE PUREBOOT_CLOCK_HZ=${_mute_hz}
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PUREBOOT_BAUD=${_mute_baud} PUREBOOT_HANDOVER)
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add_custom_command(TARGET pbapp_handover POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -O binary
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$<TARGET_FILE:pbapp_handover> $<TARGET_FILE:pbapp_handover>.bin)
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add_test(NAME pureboot.mute
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COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/test/pbmute.py
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${PB_DEVICE} $<TARGET_FILE:pureboot_sw_on_usart0> ${PUREBOOT_SIM_MCU} ${_mute_hz}
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${PUREBOOT_BASE_HEX} ${PUREBOOT_PAGE} ${_mute_baud}
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$<TARGET_FILE:pbapp_handover>.bin
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${CMAKE_CURRENT_SOURCE_DIR}/pureboot/pureboot.py
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${CMAKE_BINARY_DIR}/pbmute-work ${_mute_link})
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set_tests_properties(pureboot.mute PROPERTIES TIMEOUT 180)
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endif()
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# The second USART, driven for real on one chip: instance selection is
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# compile-checked everywhere, but only a live session proves the loader
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# initialized and polls the USART it claims to. The fixture application
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