build: the libavr pin advances past phase 6, at byte parity everywhere

The pin crosses libavr's phase 6 - the renamed system surface, the named
serial configs, the receiver-tolerance table, the paged SPM receipts -
and every loader image comes out size-identical: the full matrix on six
representative chips (the exhaustive cross product on three of them),
the stock and autobaud columns untouched, the four tsb tiers back on
their recorded floors at 510/526/638/836.

Byte parity was not free, and the two libavr defects it surfaced were
fixed there rather than absorbed here. The EEPROM write procedure's
step 2 - the SPMEN spin - had landed unconditionally and cost every
build six bytes for a wait a polled loader can never take; it is scoped
now, and the loaders state the datasheet's own omission clause
(spm_interlock::omitted, DS40002061B 8.6.3). The blocking page
erase/write grew an internal wait the tiers' settle() already provides,
so the tiers issue the command form and pureboot keeps its host-driven
sp_spm path.

What the port states rather than inherits: the stock 115200 at 16 MHz
sits +2.1 % past the receiver-tolerance table libavr now holds rates
to, so the hardware links say .allow_baud_error = true - the same
2.5 % envelope pureboot_baud_feasible() has always enforced, proven on
silicon across the fleet. rx_ready() reads readable() now.

Alongside the pin: rule 33's ASCII sweep over every source (docs keep
their typography), rule 34's InsertBraces in .clang-format with the
tree reformatted, std::array over the simavr runners' raw buffers, and
the stale Studio size in ide/README.md replaced by the claim its
check-flags gate actually holds.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

tools/pbrig.py

@@ -3,14 +3,14 @@
 
 The simulated suites (`test/pb*.py`) prove the protocol; this drives the same
 loader on real silicon, where the things a cycle-exact simulator cannot model
-live — an RC oscillator off its nominal, a reset edge that has to come from
+live - an RC oscillator off its nominal, a reset edge that has to come from
 somewhere, a serial bridge with its own idea of what a baud is.
 
 Nothing here knows a port name, a part or a programmer. Every deployment fact
 arrives from the command line or the environment, so the same script serves any
 board: see `Deployment`. As a module it is the reset/flash/talk primitives that
 `pbhw.py` builds its acceptance suite from; as a command it is the handful of
-one-shot operations worth having on a rig — most importantly `backup`, which is
+one-shot operations worth having on a rig - most importantly `backup`, which is
 the only thing standing between a fuse experiment and an unrecoverable part.
 
 Two rig facts are encoded here because they are not guessable and cost a
@@ -18,7 +18,7 @@ session each to learn:
 
 * **An ISP access resets the part**, and it runs again the moment the programmer
   releases it. That is the only reset edge available when the serial adapter's
-  DTR is not wired to reset — so a loader session begins with an ISP touch and
+  DTR is not wired to reset - so a loader session begins with an ISP touch and
   knocks immediately after, which is what `Rig.pureboot()` does.
 * **avrdude splits `-U memory:op:file:format` on colons**, so a Windows path's
   drive letter breaks the spec. Every file argument is therefore passed as a
@@ -63,7 +63,7 @@ def bitclock_for(hz: int) -> str:
     """A safe ISP bitclock for a part *currently running* at `hz`.
 
     SCK must stay under a quarter of the target clock, so the bitclock follows
-    the clock in force — not the one about to be fused in. Halving that ceiling
+    the clock in force - not the one about to be fused in. Halving that ceiling
     again costs nothing on a link that moves a few hundred bytes and buys margin
     against an oscillator that is already known to be off its nominal.
     """
@@ -138,7 +138,7 @@ class Deployment:
 
 
 def load_pureboot(path: pathlib.Path = DEFAULT_PUREBOOT):
-    """The host tool as a module — its Port and Loader, not a subprocess.
+    """The host tool as a module - its Port and Loader, not a subprocess.
 
     Used where a subprocess cannot express what is needed: a poke followed by a
     peek in the *same* session, or a raw read at an arbitrary baud.
@@ -260,7 +260,7 @@ class Rig:
     def pureboot(self, *args: str, reset_first: bool = True, baud: int | None = None,
                  autobaud: bool | None = None, timeout: int = 300,
                  bitclock: str | None = None) -> tuple[int, str]:
-        """Reset, then knock immediately — see the module docstring.
+        """Reset, then knock immediately - see the module docstring.
 
         Returns the host tool's exit status and its combined output, so a caller
         can assert on what it printed as well as on whether it succeeded.
@@ -301,7 +301,7 @@ class Rig:
         """Listen to whatever the board is saying, at an arbitrary rate.
 
         Opening the port does not reset a board whose DTR is unwired, so this can
-        sample a running application repeatedly without disturbing it — which is
+        sample a running application repeatedly without disturbing it - which is
         what makes the rate sweep below possible.
         """
         module = load_pureboot(self.d.pureboot)
@@ -327,7 +327,7 @@ def measure_rate(rig: Rig, marker: bytes, built_baud: int, nominal_hz: int | Non
     """Find a transmitting board's true bit rate, using only the serial port.
 
     The board must be emitting something recognisable at a *fixed* cycles-per-bit
-    — `test/pbapp.cpp` built with PUREBOOT_HEARTBEAT does. Since its bit timing is
+    - `test/pbapp.cpp` built with PUREBOOT_HEARTBEAT does. Since its bit timing is
     a cycle count, its wire rate scales with its actual clock, so the host rates
     at which `marker` still decodes bracket that rate; the centre of the band is
     the answer, and with the clock the image was built for it gives the real one.
@@ -430,7 +430,7 @@ def main(argv: list[str] | None = None) -> int:
             for baud, size, hit in result["samples"]:
                 print(f"  {baud:7d} Bd  {size:5d} B  {'MARKER' if hit else ''}")
         if not result["clean"]:
-            print(f"no capture contained {args.marker!r} at any rate — is the board "
+            print(f"no capture contained {args.marker!r} at any rate - is the board "
                   f"transmitting, and on the pin this port is wired to?")
             return 1
         print(f"clean band  {result['low']}..{result['high']} Bd")