build: the libavr pin advances past phase 6, at byte parity everywhere

The pin crosses libavr's phase 6 - the renamed system surface, the named
serial configs, the receiver-tolerance table, the paged SPM receipts -
and every loader image comes out size-identical: the full matrix on six
representative chips (the exhaustive cross product on three of them),
the stock and autobaud columns untouched, the four tsb tiers back on
their recorded floors at 510/526/638/836.

Byte parity was not free, and the two libavr defects it surfaced were
fixed there rather than absorbed here. The EEPROM write procedure's
step 2 - the SPMEN spin - had landed unconditionally and cost every
build six bytes for a wait a polled loader can never take; it is scoped
now, and the loaders state the datasheet's own omission clause
(spm_interlock::omitted, DS40002061B 8.6.3). The blocking page
erase/write grew an internal wait the tiers' settle() already provides,
so the tiers issue the command form and pureboot keeps its host-driven
sp_spm path.

What the port states rather than inherits: the stock 115200 at 16 MHz
sits +2.1 % past the receiver-tolerance table libavr now holds rates
to, so the hardware links say .allow_baud_error = true - the same
2.5 % envelope pureboot_baud_feasible() has always enforced, proven on
silicon across the fleet. rx_ready() reads readable() now.

Alongside the pin: rule 33's ASCII sweep over every source (docs keep
their typography), rule 34's InsertBraces in .clang-format with the
tree reformatted, std::array over the simavr runners' raw buffers, and
the stale Studio size in ide/README.md replaced by the claim its
check-flags gate actually holds.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

test/test_planner.py

@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-"""Host-tool unit tests — the planning and policy logic, no simulator:
+"""Host-tool unit tests - the planning and policy logic, no simulator:
 programming orders and their recovery properties, the reset-vector surgery,
 the staging composition, the boot-fuse decode, and the update preflight over
 fuse combinations simavr cannot model.
@@ -76,7 +76,7 @@ def main():
         "newer tool",
     )
 
-    # mega_boot: BOOTSZ words and the BOOTRST sense per chip — the fuse byte
+    # mega_boot: BOOTSZ words and the BOOTRST sense per chip - the fuse byte
     # index (EXTENDED on the x8 line except the m328s' HIGH, HIGH elsewhere)
     # and the per-family ladders (Atmel-2486/2466/2503/2545/8271/DS40002065/
     # 8272/8011/2593/42719). Synthetic 'F' replies: only the boot byte
@@ -114,15 +114,15 @@ def main():
                 fail(f"mega_boot {signature[1]:02x}{signature[2]:02b} unprogrammed: {prog} {at:#07x}")
 
     # Word-addressed info decode: the 1284P's base and page ride the wire
-    # scaled — a 17-bit base halved into the block's two bytes, a 256-byte page
-    # spelled 0 — and its slot is the same 512 bytes as everywhere else, so its
+    # scaled - a 17-bit base halved into the block's two bytes, a 256-byte page
+    # spelled 0 - and its slot is the same 512 bytes as everywhere else, so its
     # staging slot lands inside the 1 KiB minimum boot section.
     big = info_of(pb, 0x1FE00, 0, False, 0x20000, signature=(0x1E, 0x97, 0x05), word_flash=True)
     if big.page != 256 or big.base != 0x1FE00 or big.stage != 0x1FC00:
         fail(f"word-addressed info decode: page {big.page}, base {big.base:#x}, stage {big.stage:#x}")
 
     # Surgery: word 0 lands on the loader, the trampoline on the original
-    # entry — checked with an independent decoder.
+    # entry - checked with an independent decoder.
     app = bytes((0xC0 | 0x00, 0xC0)) + bytes((0x12,)) * 300  # rjmp .+0x00C0... entry word 0xC0C0
     entry = rjmp_decode(app[0] | (app[1] << 8), 0, tiny.flash_size // 2)
     pages = pb.plan_flash(app, tiny)
@@ -158,7 +158,7 @@ def main():
 
     # Staging content: the identical image plus the through-word on a
     # patched-vector chip; hard size clamps either way.
-    image = bytes(range(256)) * 2  # 512 B — too big for a tiny slot
+    image = bytes(range(256)) * 2  # 512 B - too big for a tiny slot
     expect_error("tiny staging size", lambda: pb.staging_content(image, tiny), "510")
     staged = pb.staging_content(image[:508], tiny)
     through = staged[510] | (staged[511] << 8)
@@ -170,7 +170,7 @@ def main():
 
     # The image stamp: found in a synthetic binary, absent in noise. pureboot
     # 5 stamps the magic, its version and the signature, and the geometry is
-    # looked up from there — so what comes back must equal what a live device
+    # looked up from there - so what comes back must equal what a live device
     # of the same chip reports.
     stamp = bytes((0x50, 0x42, pb.NEWEST_LOADER)) + bytes(tiny.signature)
     binary = bytes((0xAA,)) * 10 + stamp + bytes((0xBB,)) * 10
@@ -228,7 +228,7 @@ def main():
 
     # The 1284s' smallest boot section (512 words) is exactly the resident
     # slot plus its staging slot, so self-update is possible at the minimum
-    # BOOTSZ — no fuse step up, the 644's geometry. That holds only while a
+    # BOOTSZ - no fuse step up, the 644's geometry. That holds only while a
     # slot is 512 B: at 1 KiB the staging slot would fall outside the section
     # and the preflight would refuse.
     notes = pb.update_preflight(bytes((0xAA,)) * 8 + big.raw, big, fuses(0xFE))
@@ -291,7 +291,7 @@ def main():
     if device.writes != pb.RETRIES + 1:
         fail(f"unrepairable page took {device.writes} writes, expected {pb.RETRIES + 1}")
 
-    # The knock handshake against a device that is not listening yet — the
+    # The knock handshake against a device that is not listening yet - the
     # state a port open leaves behind: it resets the chip into a fresh
     # activation window while the previous session's prompt is still in
     # flight, so the first knock is lost and a prompt arrives anyway.