build: the libavr pin advances past phase 6, at byte parity everywhere

The pin crosses libavr's phase 6 - the renamed system surface, the named
serial configs, the receiver-tolerance table, the paged SPM receipts -
and every loader image comes out size-identical: the full matrix on six
representative chips (the exhaustive cross product on three of them),
the stock and autobaud columns untouched, the four tsb tiers back on
their recorded floors at 510/526/638/836.

Byte parity was not free, and the two libavr defects it surfaced were
fixed there rather than absorbed here. The EEPROM write procedure's
step 2 - the SPMEN spin - had landed unconditionally and cost every
build six bytes for a wait a polled loader can never take; it is scoped
now, and the loaders state the datasheet's own omission clause
(spm_interlock::omitted, DS40002061B 8.6.3). The blocking page
erase/write grew an internal wait the tiers' settle() already provides,
so the tiers issue the command form and pureboot keeps its host-driven
sp_spm path.

What the port states rather than inherits: the stock 115200 at 16 MHz
sits +2.1 % past the receiver-tolerance table libavr now holds rates
to, so the hardware links say .allow_baud_error = true - the same
2.5 % envelope pureboot_baud_feasible() has always enforced, proven on
silicon across the fleet. rx_ready() reads readable() now.

Alongside the pin: rule 33's ASCII sweep over every source (docs keep
their typography), rule 34's InsertBraces in .clang-format with the
tree reformatted, std::array over the simavr runners' raw buffers, and
the stale Studio size in ide/README.md replaced by the claim its
check-flags gate actually holds.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

test/pbupdate.py

@@ -4,8 +4,8 @@ itself with a re-timed build, and every power-fail phase is rehearsed by
 killing the device mid-write, restarting it from its flash dump, and letting
 a re-run complete the update.
 
-The boot-sectioned megas run the BOOTRST-unprogrammed profile — reset boots
-the application, whose 'L' is the application-owned loader entry — with
+The boot-sectioned megas run the BOOTRST-unprogrammed profile - reset boots
+the application, whose 'L' is the application-owned loader entry - with
 --assume-fuses standing in for the fuse read simavr cannot model.
 
 Usage: pbupdate.py <device_bin> <pureboot_elf> <update_elf> <mcu> <hz>
@@ -39,8 +39,8 @@ class PowerFail(Exception):
 
 def assumed_fuses(pb, image):
     """Synthetic 'F' bytes for --assume-fuses: the smallest boot section
-    covering both the resident and the staging slot (two slots — what a
-    self-update needs), BOOTRST unprogrammed — the per-chip BOOTSZ ladder
+    covering both the resident and the staging slot (two slots - what a
+    self-update needs), BOOTRST unprogrammed - the per-chip BOOTSZ ladder
     and fuse byte come from the tool's own table, keyed by the update
     image's embedded signature."""
     info = pb.image_info(image)
@@ -138,7 +138,7 @@ def main():
     device = pbsim.Device(device_bin, elf, mcu, hz, base_hex, page, baud, dump, reset_hex=reset_hex)
     final = "v0"
     try:
-        # The application first — its planner output is the restore truth.
+        # The application first - its planner output is the restore truth.
         pbsim.run_tool(tool, device.pty, baud, "--flash", app_bin, "--stay")
         port, loader = connect(device)
         app_pages = pb.plan_flash(open(app_bin, "rb").read(), loader.info)
@@ -167,7 +167,7 @@ def main():
         # direction so the flash is never already at its target. The mega's
         # mid-resident-rewrite loss is exercised as a host crash instead:
         # with BOOTRST unprogrammed and the resident mid-erase, a power loss
-        # there has no reset path into the staging copy — the documented
+        # there has no reset path into the staging copy - the documented
         # cost of that profile (README).
         for kill_region, kill_hits, kill_device in (
             ("stage", 2, True),