build: the libavr pin advances past phase 6, at byte parity everywhere

The pin crosses libavr's phase 6 - the renamed system surface, the named
serial configs, the receiver-tolerance table, the paged SPM receipts -
and every loader image comes out size-identical: the full matrix on six
representative chips (the exhaustive cross product on three of them),
the stock and autobaud columns untouched, the four tsb tiers back on
their recorded floors at 510/526/638/836.

Byte parity was not free, and the two libavr defects it surfaced were
fixed there rather than absorbed here. The EEPROM write procedure's
step 2 - the SPMEN spin - had landed unconditionally and cost every
build six bytes for a wait a polled loader can never take; it is scoped
now, and the loaders state the datasheet's own omission clause
(spm_interlock::omitted, DS40002061B 8.6.3). The blocking page
erase/write grew an internal wait the tiers' settle() already provides,
so the tiers issue the command form and pureboot keeps its host-driven
sp_spm path.

What the port states rather than inherits: the stock 115200 at 16 MHz
sits +2.1 % past the receiver-tolerance table libavr now holds rates
to, so the hardware links say .allow_baud_error = true - the same
2.5 % envelope pureboot_baud_feasible() has always enforced, proven on
silicon across the fleet. rx_ready() reads readable() now.

Alongside the pin: rule 33's ASCII sweep over every source (docs keep
their typography), rule 34's InsertBraces in .clang-format with the
tree reformatted, std::array over the simavr runners' raw buffers, and
the stale Studio size in ide/README.md replaced by the claim its
check-flags gate actually holds.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

test/pbselfwrite.py

@@ -3,7 +3,7 @@
 loader is executing from.
 
 pureboot 9 dropped the running-slot write guard, so this command is now
-permitted — that is what lets a resident copy plant something in its own slot,
+permitted - that is what lets a resident copy plant something in its own slot,
 which on a chip whose boot section *is* the loader slot is the only route a
 self-update has. Permitted means the loader must actually do it, and the only
 honest proof is the flash afterwards.
@@ -72,12 +72,12 @@ def main():
             fail("the loader did not re-prompt after refusing the erase")
         alive = loader.read_flash(base, 8)
         if alive == b"\xff" * 8:
-            fail("the refused erase happened anyway — the running page reads erased")
+            fail("the refused erase happened anyway - the running page reads erased")
 
         # Green: the identical command, correctly sealed. Nothing is required
         # of the link from here on. The verdict is *issued* before the SPM, but
         # the erase takes the code that would have finished saying it, and how
-        # much of it survives is the chip's business — an erase removes one page
+        # much of it survives is the chip's business - an erase removes one page
         # and nothing else, so a loader whose command loop lives past the page
         # erased will prompt as usual where one with 128-byte pages goes with
         # the stub. None of that is the claim. The claim is that the erase
@@ -95,7 +95,7 @@ def main():
     # Ground truth: the simulator's flash, not the loader's opinion of it.
     flash = open(dump, "rb").read()
     if flash[base : base + page] != b"\xff" * page:
-        fail("the sealed erase did not reach flash — the running page is intact")
+        fail("the sealed erase did not reach flash - the running page is intact")
     print("pbselfwrite: the running slot is refused unsealed and erased sealed")