build: the libavr pin advances past phase 6, at byte parity everywhere

The pin crosses libavr's phase 6 - the renamed system surface, the named
serial configs, the receiver-tolerance table, the paged SPM receipts -
and every loader image comes out size-identical: the full matrix on six
representative chips (the exhaustive cross product on three of them),
the stock and autobaud columns untouched, the four tsb tiers back on
their recorded floors at 510/526/638/836.

Byte parity was not free, and the two libavr defects it surfaced were
fixed there rather than absorbed here. The EEPROM write procedure's
step 2 - the SPMEN spin - had landed unconditionally and cost every
build six bytes for a wait a polled loader can never take; it is scoped
now, and the loaders state the datasheet's own omission clause
(spm_interlock::omitted, DS40002061B 8.6.3). The blocking page
erase/write grew an internal wait the tiers' settle() already provides,
so the tiers issue the command form and pureboot keeps its host-driven
sp_spm path.

What the port states rather than inherits: the stock 115200 at 16 MHz
sits +2.1 % past the receiver-tolerance table libavr now holds rates
to, so the hardware links say .allow_baud_error = true - the same
2.5 % envelope pureboot_baud_feasible() has always enforced, proven on
silicon across the fleet. rx_ready() reads readable() now.

Alongside the pin: rule 33's ASCII sweep over every source (docs keep
their typography), rule 34's InsertBraces in .clang-format with the
tree reformatted, std::array over the simavr runners' raw buffers, and
the stale Studio size in ide/README.md replaced by the claim its
check-flags gate actually holds.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

test/pbmute.py

@@ -6,7 +6,7 @@ application hands over with that USART still enabled: TXEN keeps the USART
 owning the pin, so the bit-banged transmitter's port writes go nowhere and the
 loader receives and obeys while answering nothing. The link's init releases it.
 
-The state is reached the way silicon reaches it — an application that sets up
+The state is reached the way silicon reaches it - an application that sets up
 its USART and jumps in with no reset between, so nothing clears UCSRnB for it.
 The pin ownership itself is modelled by the device runner: simavr wires a
 USART through IRQs alone and never takes the pin from the port, so without
@@ -35,7 +35,7 @@ def main():
     import pureboot as pb
 
     if "@" not in link:
-        fail(f"the link {link} names no owning USART — nothing would be under test")
+        fail(f"the link {link} names no owning USART - nothing would be under test")
     # A shared line (RX == TX) echoes the host's own bytes; discard them the
     # way the shipped --one-wire mode does.
     one_wire = re.fullmatch(r"sw:([A-H][0-7]),\1@[01]", link) is not None
@@ -63,7 +63,7 @@ def main():
         try:
             loader.connect(25)
         except pb.Error as error:
-            fail(f"the loader never answered after the hand-over — the USART still owns its TX pin ({error})")
+            fail(f"the loader never answered after the hand-over - the USART still owns its TX pin ({error})")
         if loader.info.version != resident:
             fail(f"identity changed across the hand-over: {resident} then {loader.info.version}")