build: the libavr pin advances past phase 6, at byte parity everywhere
The pin crosses libavr's phase 6 - the renamed system surface, the named serial configs, the receiver-tolerance table, the paged SPM receipts - and every loader image comes out size-identical: the full matrix on six representative chips (the exhaustive cross product on three of them), the stock and autobaud columns untouched, the four tsb tiers back on their recorded floors at 510/526/638/836. Byte parity was not free, and the two libavr defects it surfaced were fixed there rather than absorbed here. The EEPROM write procedure's step 2 - the SPMEN spin - had landed unconditionally and cost every build six bytes for a wait a polled loader can never take; it is scoped now, and the loaders state the datasheet's own omission clause (spm_interlock::omitted, DS40002061B 8.6.3). The blocking page erase/write grew an internal wait the tiers' settle() already provides, so the tiers issue the command form and pureboot keeps its host-driven sp_spm path. What the port states rather than inherits: the stock 115200 at 16 MHz sits +2.1 % past the receiver-tolerance table libavr now holds rates to, so the hardware links say .allow_baud_error = true - the same 2.5 % envelope pureboot_baud_feasible() has always enforced, proven on silicon across the fleet. rx_ready() reads readable() now. Alongside the pin: rule 33's ASCII sweep over every source (docs keep their typography), rule 34's InsertBraces in .clang-format with the tree reformatted, std::array over the simavr runners' raw buffers, and the stale Studio size in ide/README.md replaced by the claim its check-flags gate actually holds. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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@@ -7,6 +7,7 @@
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// SPM genuinely writes avr->flash on the mega cores, so on exit (or SIGTERM)
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// we dump the flash image to a file for a ground-truth cross-check against
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// what the client read back through the bootloader.
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#include <array>
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#include <csignal>
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#include <cstdint>
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#include <cstdio>
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@@ -17,7 +18,7 @@
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#include <unistd.h>
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// The parts headers (uart_pty.h) carry no C++ linkage guards of their own,
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// unlike simavr's core headers — the block covers both harmlessly.
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// unlike simavr's core headers - the block covers both harmlessly.
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extern "C" {
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#include "avr_uart.h"
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#include "sim_avr.h"
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@@ -75,11 +76,11 @@ int main(int argc, char *argv[])
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return 1;
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}
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// An image that runs past flash end cannot execute on hardware, and a
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// naive copy of it would smash the heap beyond avr->flash — after which
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// naive copy of it would smash the heap beyond avr->flash - after which
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// the simulation misbehaves in ways that point everywhere but here.
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// Refuse it loudly instead.
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if (boot_base + fw.flashsize > avr->flashend + 1) {
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std::println(stderr, "device: {} B at {:#x} runs past flash end {:#x} — image does not fit its slot",
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std::println(stderr, "device: {} B at {:#x} runs past flash end {:#x} - image does not fit its slot",
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fw.flashsize, boot_base, avr->flashend);
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return 1;
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}
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@@ -94,13 +95,13 @@ int main(int argc, char *argv[])
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if (cfg) {
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std::uint32_t app_end = boot_base - 128; // config page sits directly below the boot code
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for (int i = 0; cfg[i] && cfg[i + 1]; i += 2) {
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char b[3] = {cfg[i], cfg[i + 1], 0};
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avr->flash[app_end + i / 2] = static_cast<std::uint8_t>(std::strtoul(b, nullptr, 16));
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const std::array<char, 3> pair = {cfg[i], cfg[i + 1], 0};
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avr->flash[app_end + i / 2] = static_cast<std::uint8_t>(std::strtoul(pair.data(), nullptr, 16));
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}
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}
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// POLL_SLEEP makes simavr usleep(1) on every status-register read while the
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// UART is idle — a host-CPU-saving hack that models no hardware and paces a
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// UART is idle - a host-CPU-saving hack that models no hardware and paces a
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// tight-polling loader (one that releases TX between bytes, as one-wire does)
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// in real time, distorting protocol timing. Clear it so the loader runs at
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// true cycle speed.
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@@ -119,8 +120,9 @@ int main(int argc, char *argv[])
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for (;;) {
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int state = avr_run(avr);
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if (state == cpu_Done || state == cpu_Crashed)
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if (state == cpu_Done || state == cpu_Crashed) {
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break;
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}
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}
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finish(0);
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}
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