build: the libavr pin advances past phase 6, at byte parity everywhere

The pin crosses libavr's phase 6 - the renamed system surface, the named
serial configs, the receiver-tolerance table, the paged SPM receipts -
and every loader image comes out size-identical: the full matrix on six
representative chips (the exhaustive cross product on three of them),
the stock and autobaud columns untouched, the four tsb tiers back on
their recorded floors at 510/526/638/836.

Byte parity was not free, and the two libavr defects it surfaced were
fixed there rather than absorbed here. The EEPROM write procedure's
step 2 - the SPMEN spin - had landed unconditionally and cost every
build six bytes for a wait a polled loader can never take; it is scoped
now, and the loaders state the datasheet's own omission clause
(spm_interlock::omitted, DS40002061B 8.6.3). The blocking page
erase/write grew an internal wait the tiers' settle() already provides,
so the tiers issue the command form and pureboot keeps its host-driven
sp_spm path.

What the port states rather than inherits: the stock 115200 at 16 MHz
sits +2.1 % past the receiver-tolerance table libavr now holds rates
to, so the hardware links say .allow_baud_error = true - the same
2.5 % envelope pureboot_baud_feasible() has always enforced, proven on
silicon across the fleet. rx_ready() reads readable() now.

Alongside the pin: rule 33's ASCII sweep over every source (docs keep
their typography), rule 34's InsertBraces in .clang-format with the
tree reformatted, std::array over the simavr runners' raw buffers, and
the stale Studio size in ide/README.md replaced by the claim its
check-flags gate actually holds.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

test/check_pi.py

@@ -2,12 +2,12 @@
 """Position-independence lint: the property that lets the identical image run
 from any slot, asserted from the built ELF and its object.
 
-  1. No absolute jmp/call — -mrelax normally guarantees it, but a branch that
+  1. No absolute jmp/call - -mrelax normally guarantees it, but a branch that
      grows out of relaxation range would break it silently.
   2. Nothing flash-resident to address: the image is .text alone, so there is
      no table whose runtime address has to be reconstructed.
   3. The image is byte-identical when linked at a different base. This is
-     position independence itself rather than a proxy for it — an absolute
+     position independence itself rather than a proxy for it - an absolute
      address anywhere in the image would move with the link and show up as a
      differing byte.