build: the libavr pin advances past phase 6, at byte parity everywhere

The pin crosses libavr's phase 6 - the renamed system surface, the named
serial configs, the receiver-tolerance table, the paged SPM receipts -
and every loader image comes out size-identical: the full matrix on six
representative chips (the exhaustive cross product on three of them),
the stock and autobaud columns untouched, the four tsb tiers back on
their recorded floors at 510/526/638/836.

Byte parity was not free, and the two libavr defects it surfaced were
fixed there rather than absorbed here. The EEPROM write procedure's
step 2 - the SPMEN spin - had landed unconditionally and cost every
build six bytes for a wait a polled loader can never take; it is scoped
now, and the loaders state the datasheet's own omission clause
(spm_interlock::omitted, DS40002061B 8.6.3). The blocking page
erase/write grew an internal wait the tiers' settle() already provides,
so the tiers issue the command form and pureboot keeps its host-driven
sp_spm path.

What the port states rather than inherits: the stock 115200 at 16 MHz
sits +2.1 % past the receiver-tolerance table libavr now holds rates
to, so the hardware links say .allow_baud_error = true - the same
2.5 % envelope pureboot_baud_feasible() has always enforced, proven on
silicon across the fleet. rx_ready() reads readable() now.

Alongside the pin: rule 33's ASCII sweep over every source (docs keep
their typography), rule 34's InsertBraces in .clang-format with the
tree reformatted, std::array over the simavr runners' raw buffers, and
the stale Studio size in ide/README.md replaced by the claim its
check-flags gate actually holds.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

pureboot/CMakeLists.txt

@@ -1,5 +1,5 @@
 # pureboot as a consumable CMake unit: the per-chip geometry, the default baud
-# ladder, and pureboot_add_loader() — the one way a loader target is created.
+# ladder, and pureboot_add_loader() - the one way a loader target is created.
 # A downstream project brings its usual libavr setup (the `libavr` target and
 # the LIBAVR_MCU toolchain preset), adds this directory, and states its
 # deployment; every argument is optional (README.md):
@@ -9,7 +9,7 @@
 
 # Per-family geometry, deployment defaults, and the linker wrap the PC modulo
 # needs. The slot is 512 bytes on every chip. The USART flags mirror the
-# hardware inventory the loader's own static asserts check — the plain 644 is
+# hardware inventory the loader's own static asserts check - the plain 644 is
 # the x4 family's one single-USART die (Atmel-2593).
 set(_pb_has_usart 1)
 set(_pb_has_usart1 0)
@@ -107,7 +107,7 @@ set(_pb_slot 512)
 math(EXPR _pb_base "${_pb_flash} - ${_pb_slot}")
 math(EXPR _pb_base_hex "${_pb_base}" OUTPUT_FORMAT HEXADECIMAL)
 # Patched-vector chips hand over through the trampoline word below the slot,
-# which is also the slot's own last word — their budget is slot − 2.
+# which is also the slot's own last word - their budget is slot - 2.
 if(LIBAVR_MCU MATCHES "^atmega" AND NOT LIBAVR_MCU MATCHES "^atmega48")
 	set(_pb_app 0)
 	set(_pb_limit ${_pb_slot})
@@ -118,7 +118,7 @@ endif()
 
 # The pins each USART owns. A bit-banged link deployed on them has to release
 # that USART before it can drive the line, and those instructions are the one
-# way the choice of pins moves the image — so a size matrix needs them as an
+# way the choice of pins moves the image - so a size matrix needs them as an
 # axis even though pins are otherwise immediate operands. Uniform across every
 # mega libavr covers: USART0 (the classics' un-numbered USART included) on
 # PD0/PD1, USART1 on PD2/PD3.
@@ -233,7 +233,7 @@ function(pureboot_default_baud clock software outvar)
 		endif()
 	endforeach()
 	message(FATAL_ERROR "pureboot: no standard baud rate fits a ${clock} Hz clock within 2.5 % "
-	        "— pass BAUD <rate> to deploy a non-standard one")
+	        " - pass BAUD <rate> to deploy a non-standard one")
 endfunction()
 
 # pureboot_add_loader(<name> [CLOCK <hz>] [BAUD <bd>]
@@ -245,12 +245,12 @@ endfunction()
 # <name>.bin for --update-loader). The resolved deployment is stamped on the
 # target as PUREBOOT_HZ / PUREBOOT_BAUD / PUREBOOT_LINK (the link spelled
 # usart0, usart1, or sw:<RX>,<TX> with a trailing @<n> where those pins are a
-# USART's own) — what a test harness speaks to it with.
+# USART's own) - what a test harness speaks to it with.
 #
 # HALF_DUPLEX is the one-wire deployment, per backend: on the hardware USART
 # it enables the library's .half_duplex turn-around (RXD and TXD tied
 # together off-chip); on a software or autobaud link it puts both directions
-# on the RX pin — the same thing RX == TX spells directly.
+# on the RX pin - the same thing RX == TX spells directly.
 #
 # SERIAL autobaud measures the host's bit timing at run time, so the image
 # carries no clock and no baud: CLOCK and BAUD are not build parameters there,
@@ -260,7 +260,7 @@ endfunction()
 #
 # OSCCAL bakes a measured oscillator trim into the loader (README.md: the
 # RC-oscillator deployment answer): the byte is written at the top of run(),
-# so every reset path — the watchdog hand-over included — runs on the
+# so every reset path - the watchdog hand-over included - runs on the
 # corrected clock. Orthogonal to the backend: an autobaud build may carry it
 # purely for the application's benefit, its own link being clock-free. No
 # value, no code.
@@ -310,7 +310,7 @@ function(pureboot_add_loader name)
 		if(PB_SERIAL STREQUAL "auto")
 			if(_usart AND (PB_RX OR PB_TX))
 				message(WARNING "pureboot_add_loader(${name}): RX/TX apply to the software UART, "
-				        "which auto does not pick on ${LIBAVR_MCU} — SERIAL software to force it")
+				        "which auto does not pick on ${LIBAVR_MCU} - SERIAL software to force it")
 			endif()
 			if(_usart)
 				set(_link usart0)
@@ -347,7 +347,7 @@ function(pureboot_add_loader name)
 			else()
 				set(_serial_defines PUREBOOT_SOFT_SERIAL PUREBOOT_RX=${PB_RX} PUREBOOT_TX=${PB_TX})
 			endif()
-			# sw:<RX>,<TX> as port letter and bit, upcased — with @<n> where
+			# sw:<RX>,<TX> as port letter and bit, upcased - with @<n> where
 			# the TX pin is a USART's own TXD, since a harness driving that
 			# link has to know the USART owns the pin until the loader
 			# releases it.
@@ -365,8 +365,8 @@ function(pureboot_add_loader name)
 				set(_link "${_link}@1")
 			elseif(PB_TX STREQUAL PB_RX AND _usart AND PB_RX STREQUAL _rx0)
 				# One-wire on a USART's RXD: RXEN forces that pin's direction
-				# (§20.7.3), so the driven shared pin is held exactly like a
-				# TXD — the harness models the hold either way.
+				# (section 20.7.3), so the driven shared pin is held exactly like a
+				# TXD - the harness models the hold either way.
 				set(_link "${_link}@0")
 			elseif(PB_TX STREQUAL PB_RX AND _usart1 AND PB_RX STREQUAL _rx1)
 				set(_link "${_link}@1")
@@ -403,12 +403,12 @@ function(pureboot_add_loader name)
 	# byte-stream loops' counters into end-pointer forms that cost registers
 	# (-fno-ivopts, -fno-split-wide-types), leaves register pressure on the
 	# table with the default allocator (-fira-algorithm=priority), and keeps
-	# expression temporaries in registers (-fno-tree-ter) — but every loop body
+	# expression temporaries in registers (-fno-tree-ter) - but every loop body
 	# here contains a call, so a register held across it costs more than the
 	# load-immediate it saves. The set is fitted to the loader's body and has to
 	# be re-measured when that body changes: -fno-move-loop-invariants belonged
 	# here while the command loop carried four transfer bodies and costs bytes
-	# now that it carries one, and -fno-ivopts is fitted per backend — an
+	# now that it carries one, and -fno-ivopts is fitted per backend - an
 	# autobaud body needs ivopts to keep the calibration countdown a single
 	# induction variable (without it the counter is duplicated and the
 	# measurement loop runs 9 cycles instead of its contracted 7), while the