pureboot 3: a 512-byte slot on every chip, the 1284s included
The word-addressed 1284s were the one family deploying in a 1 KiB slot, because the far-flash machinery (ELPM reads, RAMPZ page commands, a word-addressed wire) did not fit 512 B. It does now: 478 B stock, 494 B in the heaviest configuration the build can produce. They take the 644s' geometry, where the smallest boot section holds the resident slot and its staging slot together. The loader's version goes to 3; the host tool did not change, so its own version stays 2 and only the window it speaks widens. Most of the saving is one restructure. The info block and a flash read are the same act, so giving all four streamed commands one address-and-count path leaves exactly one call site for the flash streamer: it inlines into the never-returning command loop and its 24-bit cursor stops being saved and restored around every transmit. Around it, the ack byte moved out of line, the wire's byte pair is bit_cast into the word it already is, the fuse loop ends on its count, the info block's in-slot offset is taken as the one-byte relocation it is, and -fno-expensive-optimizations gives way to -fno-move-loop-invariants -fno-tree-ter. Every chip shrank 14-18 B. The size matrix grew the axes it was missing: the USART1 instance across the whole clock ladder, and the shape a slow baud gives a software UART — past 255 delay iterations libavr takes the 16-bit delay loop, which the ladder default never selects and which was 4 B over the 1284's slot the first time it was built. The protocol fixture stopped deriving the loader entry from the flash size; on the 1284s it had been jumping a slot low and reaching the loader only because erased flash walked it up. Docs and comments were consolidated across the port in the same pass: the README carries a per-chip size table instead of prose, and prose that restated the code is gone — 190 lines, no behaviour with it. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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@@ -1,27 +1,16 @@
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# pureboot as a consumable CMake unit: the per-chip geometry, the default
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# baud ladder, and pureboot_add_loader() — the one way a loader target is
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# created, both by this port's own build and by a downstream project. A
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# downstream project brings its usual libavr setup (the `libavr` target and
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# pureboot as a consumable CMake unit: the per-chip geometry, the default baud
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# ladder, and pureboot_add_loader() — the one way a loader target is created.
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# A downstream project brings its usual libavr setup (the `libavr` target and
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# the LIBAVR_MCU toolchain preset), adds this directory, and states its
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# deployment:
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# deployment; every argument is optional (README.md):
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#
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# add_subdirectory(bootloader/pureboot)
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# pureboot_add_loader(myboot CLOCK 1000000 SERIAL software TX pb1 RX pb5)
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#
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# Every argument is optional — CLOCK defaults to the family assumption
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# below, BAUD to the fastest standard rate the clock reaches within 2.5 %
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# (the ladder), SERIAL to the chip's hardware USART where it has one
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# (`hardware`/`software` force a backend, USART 1 picks the second
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# instance), RX/TX to pb0/pb1 for the software UART, TIMEOUT to 8 s.
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# Infeasible picks fail the build by name: libavr's baud-error and
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# software-UART cycle-floor static asserts re-check whatever is passed.
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# Per-family geometry: flash/page/EEPROM sizes and the linker wrap the PC
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# modulo needs, the loader slot (each chip's smallest boot sector — 1 KiB on
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# the word-addressed 1284s), and the deployment defaults (crystal assumption
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# on the megas, calibrated RC on the tinies). The USART flags mirror the
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# hardware inventory the loader's own static asserts check (the plain 644 is
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# the x4 family's one single-USART die, Atmel-2593).
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# Per-family geometry, deployment defaults, and the linker wrap the PC modulo
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# needs. The slot is 512 bytes on every chip. The USART flags mirror the
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# hardware inventory the loader's own static asserts check — the plain 644 is
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# the x4 family's one single-USART die (Atmel-2593).
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set(_pb_has_usart 1)
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set(_pb_has_usart1 0)
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if(LIBAVR_MCU MATCHES "^attiny13a?$")
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@@ -91,10 +80,9 @@ elseif(LIBAVR_MCU MATCHES "^atmega324(a|p|pa)$")
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set(_pb_eeprom 1024)
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set(_pb_has_usart1 1)
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elseif(LIBAVR_MCU MATCHES "^atmega644(a|p|pa)?$")
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# 64 KiB is exactly the 16-bit byte space: plain LPM reaches everything,
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# and the smallest boot section (1 KiB) holds the loader and its staging
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# slot together (see README.md). The plain 644 is the family's one
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# single-USART die.
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# 64 KiB is exactly the 16-bit byte space, so plain LPM still reaches
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# everything and the wire stays byte-addressed. The plain 644 is the
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# family's one single-USART die.
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set(_pb_flash 65536)
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set(_pb_wrap -Wl,--pmem-wrap-around=64k)
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set(_pb_page 256)
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@@ -104,33 +92,25 @@ elseif(LIBAVR_MCU MATCHES "^atmega644(a|p|pa)?$")
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set(_pb_has_usart1 1)
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endif()
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elseif(LIBAVR_MCU MATCHES "^atmega1284p?$")
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# 128 KiB: wire flash addresses are word addresses, reads go through
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# ELPM, and the PC's modulo wrap exceeds what --pmem-wrap-around models.
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# The slot is 1 KiB — this chip's own smallest boot sector; the far
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# machinery cannot fit 512 B (see README.md).
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# 128 KiB: wire addresses are words, reads go through ELPM, and the PC's
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# modulo wrap exceeds what --pmem-wrap-around models.
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set(_pb_flash 131072)
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set(_pb_wrap "")
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set(_pb_page 256)
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set(_pb_hz 16000000)
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set(_pb_eeprom 4096)
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set(_pb_slot 1024)
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set(_pb_limit 1024)
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set(_pb_has_usart1 1)
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else()
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message(FATAL_ERROR "pureboot: no geometry for ${LIBAVR_MCU}")
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endif()
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if(NOT DEFINED _pb_slot)
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set(_pb_slot 512)
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endif()
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set(_pb_slot 512)
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math(EXPR _pb_base "${_pb_flash} - ${_pb_slot}")
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math(EXPR _pb_base_hex "${_pb_base}" OUTPUT_FORMAT HEXADECIMAL)
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# Patched-vector chips hand over through the trampoline word below the slot,
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# which is also the slot's own last word — their budget is slot − 2.
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if(LIBAVR_MCU MATCHES "^atmega" AND NOT LIBAVR_MCU MATCHES "^atmega48")
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set(_pb_app 0)
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if(NOT DEFINED _pb_limit)
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set(_pb_limit ${_pb_slot})
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endif()
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set(_pb_limit ${_pb_slot})
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else()
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math(EXPR _pb_app "${_pb_base} - 2")
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math(EXPR _pb_limit "${_pb_slot} - 2")
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@@ -166,12 +146,11 @@ set(PUREBOOT_HAS_USART ${_pb_has_usart} PARENT_SCOPE)
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set(PUREBOOT_HAS_USART1 ${_pb_has_usart1} PARENT_SCOPE)
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set(PUREBOOT_SIM_MCU ${_pb_sim_mcu} PARENT_SCOPE)
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# The fastest standard rate the clock reaches within 2.5 % — the same
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# best-of-U2X-and-plain divisor search libavr's solve_baud runs, so a
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# default never trips the compile-time error it is checked against. A
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# software build additionally requires the polled receiver's 100-cycles-a-bit
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# floor (its own static assert): at low clocks the U2X divisor still reaches
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# rates the bit-banged sampler cannot, so the backend gates the ladder.
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# The fastest standard rate the clock reaches within 2.5 %, by the same
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# best-of-U2X-and-plain divisor search libavr's solve_baud runs, so a default
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# never trips the compile-time error it is checked against. A software build
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# also needs the polled receiver's 100-cycles-a-bit floor: at low clocks the
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# U2X divisor reaches rates the bit-banged sampler cannot.
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function(pureboot_default_baud clock software outvar)
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foreach(baud 115200 57600 38400 19200 9600)
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math(EXPR _cycles "${clock} / ${baud}")
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@@ -203,11 +182,10 @@ endfunction()
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# [SERIAL auto|hardware|software] [USART <n>]
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# [RX <pin>] [TX <pin>] [TIMEOUT <s>])
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#
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# Creates the loader target plus its flashable images (<name>.hex for a
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# programmer, <name>.bin for --update-loader) and stamps the resolved
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# deployment on the target: the PUREBOOT_HZ, PUREBOOT_BAUD and PUREBOOT_LINK
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# properties (the link as usart0/usart1/sw:<RX>,<TX> — what a test harness
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# needs to speak to the build).
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# The loader target plus its flashable images (<name>.hex for a programmer,
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# <name>.bin for --update-loader). The resolved deployment is stamped on the
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# target as PUREBOOT_HZ / PUREBOOT_BAUD / PUREBOOT_LINK (the link spelled
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# usart0, usart1 or sw:<RX>,<TX>) — what a test harness speaks to it with.
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function(pureboot_add_loader name)
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cmake_parse_arguments(PB "" "CLOCK;BAUD;SERIAL;USART;RX;TX;TIMEOUT" "" ${ARGN})
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if(PB_UNPARSED_ARGUMENTS)
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@@ -272,8 +250,7 @@ function(pureboot_add_loader name)
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endif()
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endforeach()
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set(_serial_defines PUREBOOT_SOFT_SERIAL PUREBOOT_RX=${PB_RX} PUREBOOT_TX=${PB_TX})
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# The link spec a test harness drives a GPIO bridge with: sw:<RX>,<TX>
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# as the port letter and bit, the loader's own pin naming upcased.
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# sw:<RX>,<TX> as port letter and bit, upcased.
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string(SUBSTRING ${PB_RX} 1 2 _rx_pin)
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string(SUBSTRING ${PB_TX} 1 2 _tx_pin)
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string(TOUPPER "sw:${_rx_pin},${_tx_pin}" _link)
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@@ -294,21 +271,22 @@ function(pureboot_add_loader name)
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add_executable(${name} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pureboot.cpp)
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target_link_libraries(${name} PRIVATE libavr)
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target_compile_definitions(${name} PRIVATE ${_defines})
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# Codegen shaping for the loader TU only, worth ~40 B on every chip and
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# what carries the far-flash 1284 build under 512. At -Os GCC otherwise
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# rewrites the byte-stream loops' counters into end-pointer forms that
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# cost registers (-fno-ivopts, -fno-split-wide-types), leaves register
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# pressure on the table with the default allocator
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# (-fira-algorithm=priority), and spends bytes on rewrites a
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# straight-line loader gains nothing from.
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# Codegen shaping for the loader TU only, worth 14–36 B depending on the
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# chip. At -Os GCC otherwise rewrites the byte-stream loops' counters into
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# end-pointer forms that cost registers (-fno-ivopts,
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# -fno-split-wide-types), leaves register pressure on the table with the
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# default allocator (-fira-algorithm=priority), and keeps loop-invariant
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# immediates and expression temporaries in registers
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# (-fno-move-loop-invariants, -fno-tree-ter) — but every loop body here
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# contains a call, so a register held across it costs more than the
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# load-immediate it saves.
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target_compile_options(${name} PRIVATE
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-fno-ivopts -fira-algorithm=priority -fno-expensive-optimizations -fno-split-wide-types)
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-fno-ivopts -fira-algorithm=priority -fno-move-loop-invariants -fno-tree-ter -fno-split-wide-types)
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target_link_options(${name} PRIVATE -nostartfiles -Wl,--section-start=.text=${_base_hex}
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-Wl,--defsym=pureboot_app=${_app} ${_wrap})
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add_custom_command(TARGET ${name} POST_BUILD COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${name}>)
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# The ELF is a container (symbols, section headers), never flashed; the
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# flashable forms sit beside it: .hex for a programmer, .bin (the slot's
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# bare bytes) for the host tool's raw path and --update-loader.
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# The ELF is a container, never flashed: .hex for a programmer, .bin (the
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# slot's bare bytes) for --update-loader.
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add_custom_command(TARGET ${name} POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -O ihex -R .eeprom
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$<TARGET_FILE:${name}> $<TARGET_FILE:${name}>.hex
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